Optical link clock receiver

Patent metadata

Field	Value
Publication number	US-10419833-B2
Application number	US-201615048915-A
Country	US
Kind code	B2
Filing date	Feb 19, 2016
Priority date	Feb 27, 2015
Publication date	Sep 17, 2019
Grant date	Sep 17, 2019

Abstract

An optical receiver of an optical link having: a photodiode coupled between a detection node and a first supply voltage rail, the photodiode being adapted to receive an optical clock signal including pulses; a switch coupled between the detection node and a second supply voltage rail; and a first transistor coupled by its main conducting nodes between the second supply voltage rail and a first output node and having its control node coupled to the detection node, wherein the switch is controlled based on a voltage at the first output node.

First claim

What is claimed is:

1. An optical receiving device of an optical link, the optical receiving device comprising:
a first optical receiver configured to convert an optical data signal into an electrical data signal using an electrical clock signal; and
a second optical receiver configured to convert an optical clock signal into said electrical clock signal, the second optical receiver comprising:
a photodiode coupled between a detection node and a first voltage rail, the photodiode being adapted to receive said optical clock signal comprising pulses;
a switch coupled between the detection node and a second voltage rail; and
a first transistor coupled by its main conducting nodes between the second voltage rail and a first output node and having its control node coupled to the detection node, wherein, when a voltage at the detection node passes a threshold level, the first transistor is rendered conductive, causing a voltage at the first output node to be asserted, and thereby causing the switch to be activated and then deactivated to reset the voltage at the detection node.

2. The optical receiving device of claim 1 , wherein the switch is coupled to the second voltage rail via a voltage offsetting device.

3. The optical receiving device of claim 2 , wherein the voltage offsetting device is a diode-connected transistor.

4. The optical receiving device of claim 1 , further comprising a second transistor coupled by its main conducting nodes between the first output node and the first voltage rail and having its control node coupled to the detection node.

5. The optical receiving device of claim 1 , wherein the first output node is coupled to the first voltage rail via the series connection of one or more further switches controlled by a clock duty cycle control signal.

6. The optical receiving device of claim 5 , wherein the series connection of one or more further switches is coupled to the first voltage rail via a further diode-connected transistor.

7. The optical receiving device of claim 1 , further comprising:
a low pass filter coupled to the first output node; and
a comparator adapted to control said switch based on a comparison between an output voltage of the low pass filter and a threshold level.

8. The optical receiving device of claim 7 , wherein said low pass filter
comprises at least one of:
a variable resistor; and
a variable capacitor.

9. The optical receiving device of claim 7 , wherein said low pass filter is an RC (resistor capacitor) filter comprising a resistor and a transistor coupled in parallel between the first output node and an intermediate node, and a variable capacitor, formed of a transistor gate, coupled to the intermediate node.

10. The optical receiving device of claim 7 , wherein the threshold voltage is generated by a duty cycle control circuit adapted to adjust the duty cycle of the clock signal.

11. The optical receiving device claim 7 , wherein the comparator is implemented by an inverter, the threshold level being the threshold voltage of the inverter.

12. The optical receiving device of claim 7 , further comprising a sequence of one or more inverters coupled to the first output node and providing said electrical clock signal.

13. The optical receiving device of claim 12 , further comprising a duty cycle detection circuit comprising:
a first low pass filter coupled to the output of a first inverter of said sequence of inverters;
a second low pass filter coupled to the output of a second inverter of said sequence of inverters, the outputs of the first and second inverters being separated by an odd number of inverters of the sequence of inverters; and
a voltage integrator adapted to generate an output voltage as a function of a voltage difference between output voltages of the first and second low pass filters, wherein the voltage integrator is adapted to control the RC value of the low pass filter.

14. The optical receiving device of claim 12 , wherein the voltage integrator comprises a current mirror having:
a first branch conducting a first current based on the output voltage of the first low pass filter; and
a second branch comprising a second transistor conducting a second current based on the first current, and a third transistor conducting a third current based on the output voltage of the second low pass filter, an intermediate node between the second and third transistors providing the output voltage of the voltage integrator.

15. A method of receiving data over an optical link comprising:
converting, using a first optical receiver, an optical data signal into an electrical data signal using an electrical clock signal; and
converting, by a second optical receiver, an optical clock signal into said electrical clock signal, comprising:
receiving, by a photodiode coupled between a detection node and a first voltage rail, an optical clock transmission signal, the detection node being coupled to a control node of a first transistor that is coupled by its main conducting nodes between a second voltage rail and a first output node; and
resetting a voltage at the detection node by activating and then deactivating a switch coupled between the detection node and a second voltage rail in response to a voltage at a first output node being asserted, the voltage at the first output node being asserted when the voltage at the detection node passes a threshold level, causing the first transistor to be rendered conductive.

Assignees

• Commissariat Energie Atomique

Inventors

• Polster Robert

Classifications

• H04L7/0075

  with photonic or optical means · CPC title

• H04L7/0008

  Synchronisation information channels, e.g. clock distribution lines · CPC title

• H04B10/6911

  Photodiode bias control, e.g. for compensating temperature variations · CPC title

• G06F1/105 Primary

  in which the distribution is at least partially optical · CPC title

• H04Q2011/0035

  using miscellaneous components, e.g. circulator, polarisation, acousto/thermo optical · CPC title