Differential voltage-mode integrate and dump photonic analog to digital converter (pADC)

Patent metadata

Field	Value
Publication number	US-9835931-B1
Application number	US-201715482498-A
Country	US
Kind code	B1
Filing date	Apr 7, 2017
Priority date	Apr 7, 2017
Publication date	Dec 5, 2017
Grant date	Dec 5, 2017

Abstract

A voltage-mode integrate-and-dump photonic ADC front-end circuit includes a current integrator for immediately integrating current pulses onto a capacitor voltage, the current pulses converted by photodetectors from optical data pulses corresponding to a received analog input signal. The circuit may include dampeners for reducing voltage ringing and resulting intersymbol interference (ISI) to preserve SNR at high data rates. The integrating capacitor may be discharged by a reset switch based on clock signals generated by a master clock; the reset switch may include a pulse width controller enabling the integrating capacitor to track and hold the integrated voltage, rather than downstream sample-and-hold amplifiers. Quantizers and other signal processors generate digital signal output by sampling and digitizing the integrated voltage output of the current integrator.

First claim

I claim:

1. A photonic analog-digital converter (pADC) front-end circuit, comprising:
at least one optical subsystem configured to generate one or more optical pulses corresponding to an analog input signal;
at least one photodetector coupled to the optical subsystem and configured to generate one or more current pulses corresponding to the one or more optical pulses;
at least one current integrator coupled to the at least one photodetector and configured to output at least one integrated voltage signal corresponding to the one or more current pulses, the at least one current integrator comprising:
an integrating capacitor configured to integrate the one or more current pulses onto a capacitor voltage; and
a reset switch coupled to the integrating capacitor and configured to reset the capacitor voltage according to a clock signal;

at least one clock subsystem coupled to the reset switch and configured to generate the at least one clock signal;
and
one or more signal processors coupled to the current integrator and configured to generate at least one digital output signal corresponding to the at least one integrated voltage signal.

2. The pADC front-end circuit of claim 1 , wherein the one or more signal processors include:
at least one amplifier configured to sample the integrated voltage signal; and
at least one quantizer coupled to the amplifier and configured to generate the at least one digital output signal based on the sampled integrated voltage signal.

3. The pADC front-end circuit of claim 2 , wherein the at least one clock signal is a first clock signal and the at least one amplifier includes a plurality of N amplifiers, where N is an integer, further comprising:
at least one demultiplexer coupled to the current integrator, the demultiplexer configured to split the at least one integrated voltage signal into N signal channels based on a second clock signal; and
at least one clock divider coupled to the demultiplexer and to the clock subsystem, the clock divider configured to determine the at least one second clock signal based on the first clock signal.

4. The pADC front-end circuit of claim 1 , further comprising:
at least one dampening circuit serially coupled to the at least one photodetector, the dampening circuit configured to reduce voltage ringing associated with the at least one integrating capacitor.

5. The pADC front-end circuit of claim 4 , wherein the dampening circuit includes at least one dampening resistor.

6. The pADC front-end circuit of claim 1 , wherein:
the at least one photodetector includes at least 1) a first photodetector coupled to the optical subsystem and configured to generate one or more in-phase current pulses corresponding to an in-phase (I) component of the one or more optical pulses and 2) a second photodetector coupled to the optical subsystem and configured to generate one or more quadrature current pulses corresponding to a quadrature (Q) component of the one or more optical pulses; and
the at least one current integrator includes at least 1) a first current integrator coupled to the at least one first photodetector and configured to output at least one in-phase integrated voltage signal corresponding to the one or more in-phase current pulses and 2) a second current integrator coupled to the at least one second photodetector and configured to output at least one quadrature integrated voltage signal corresponding to the one or more quadrature current pulses;
and
the one or more signal processors are configured to generate at least one in-phase digital output signal corresponding to the at least one in-phase integrated voltage signal and at least one quadrature digital output signal corresponding to the at least one quadrature integrated voltage signal.

7. The pADC front-end circuit of claim 1 , wherein the circuit is embodied in a receiver configured to receive the at least one analog input signal via one or more antenna elements.

8. A differential pADC front-end circuit, comprising:
a first optical subsystem configured to generate one or more first optical pulses corresponding to an analog input signal;
a second optical subsystem configured to generate one or more second optical pulses corresponding to the analog input signal;
at least one first photodetector coupled to the first optical subsystem and configured to generate one or more first current pulses corresponding to the one or more first optical pulses;
at least one second photodetector coupled to the second optical subsystem and configured to generate one or more second current pulses corresponding to the one or more second optical pulses;
at least one current integrator coupled to the first photodetector and the second photodetector and configured to output at least one of a first integrated voltage signal corresponding to the one or more first current pulses and a second integrated voltage signal corresponding to the one or more second current pulses, the at least one current integrator comprising:
an integrating capacitor configured to integrate onto a capacitor voltage at least one of the one or more first current pulses and the one or more second current pulses; and
a reset switch coupled to the integrating capacitor and configured to reset the capacitor voltage according to a clock signal;

at least one clock subsystem coupled to the reset switch and configured to generate the at least one clock signal;
at least one differential amplifier coupled to the current integrator and configured to:
receive the at least one first integrated voltage signal and the at least one second integrated voltage signal from the current integrator;
generate at least one differential voltage signal based on the first integrated voltage signal and the second integrated voltage signal;

and
one or more signal processors coupled to the differential amplifier configured to generate at least one digital output signal corresponding to the at least one differential voltage signal.

9. The differential pADC front-end circuit of claim 8 , wherein the at least one differential amplifier is a first differential amplifier and the one or more signal processors include:
at least one second differential amplifier configured to sample the differential voltage signal; and
at least one quantizer coupled to the amplifier and configured to generate the at least one digital output signal based on the sampled differential voltage signal.

10. The differential pADC front-end circuit of claim 9 , wherein the at least one clock signal is a first clock signal and the at least one differential amplifier includes a plurality of N differential amplifiers, where N is an integer, further comprising:
at least one demultiplexer coupled to the current integrator, the demultiplexer configured to split the at least one differential voltage signal into N signal channels based on a second clock signal; and
at least one clock divider coupled to the demultiplexer and to the clock subsystem, the clock divider configured to determine the at least one second clock signal based on the first clock signal.

11. The differential pADC front-end circuit of claim 8 , further comprising:
at least one dampening circuit serially coupled to one or more of the first photodetector and the second photodetector, the dampening circuit configured to reduce voltage ringing associated with the at least one integrating capacitor.

12. The differential pADC front-end circuit of claim 11 , wherein the dampening circuit includes at least one dampening resistor.

13. The differential pADC front-end circuit of claim 8 , wherein:
the at least one first photodetector is configured to generate on

Assignees

• Rockwell Collins Inc

Inventors

• Pelteku Altin E

Classifications

• G02F2001/13312

  Physics · mapped topic

• H02M2001/0041

  Electricity · mapped topic

• H02M1/092

  the control signals being transmitted optically · CPC title

• G02F1/13318

  Circuits comprising a photodetector · CPC title

• G02F7/00 Primary

  Optical analogue/digital converters · CPC title