Oxide semiconductor film and semiconductor device

Patent metadata

Field	Value
Publication number	US-10418491-B2
Application number	US-201715846518-A
Country	US
Kind code	B2
Filing date	Dec 19, 2017
Priority date	Sep 24, 2009
Publication date	Sep 17, 2019
Grant date	Sep 17, 2019

Abstract

It is an object to provide a highly reliable semiconductor device with good electrical characteristics and a display device including the semiconductor device as a switching element. In a transistor including an oxide semiconductor layer, a needle crystal group provided on at least one surface side of the oxide semiconductor layer grows in a c-axis direction perpendicular to the surface and includes an a-b plane parallel to the surface, and a portion except for the needle crystal group is an amorphous region or a region in which amorphousness and microcrystals are mixed. Accordingly, a highly reliable semiconductor device with good electrical characteristics can be formed.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a gate electrode layer;
a gate insulating layer over the gate electrode layer;
a first oxide semiconductor layer over the gate insulating layer;
a second oxide semiconductor layer over the first oxide semiconductor layer;
a source electrode and a drain electrode; and
an oxide insulating layer in contact with an upper surface of the second oxide semiconductor layer,
wherein each of the source electrode and the drain electrode are electrically connected to the first oxide semiconductor layer and the second oxide semiconductor layer,
wherein the first oxide semiconductor layer comprises first nanocrystals,
wherein the second oxide semiconductor layer comprises at least two crystals whose crystal axes are aligned, and
wherein a length of one of the two crystals in the second oxide semiconductor layer in a c-axis direction is greater than or equal to five times a length of the one of the two crystals in the second oxide semiconductor layer in a direction of an a-axis or a b-axis.

2. The semiconductor device according to claim 1 ,
wherein the length of each of the two crystals in the second oxide semiconductor layer in the direction of the a-axis or the b-axis is greater than or equal to 2 nm and less than or equal to 50 nm.

3. The semiconductor device according to claim 1 ,
wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises In, Ga and Zn.

4. The semiconductor device according to claim 1 ,
wherein the gate insulating layer is a laminate film of silicon nitride and silicon oxynitride.

5. The semiconductor device according to claim 1 ,
wherein the oxide insulating layer comprises silicon oxide or aluminum oxide.

6. A semiconductor device comprising:
a gate electrode layer;
a gate insulating layer over the gate electrode layer;
a first oxide semiconductor layer over the gate insulating layer;
a second oxide semiconductor layer over the first oxide semiconductor layer;
a source electrode and a drain electrode; and
an oxide insulating layer in contact with an upper surface of the second oxide semiconductor layer,
wherein each of the source electrode and the drain electrode are electrically connected to the first oxide semiconductor layer and the second oxide semiconductor layer,
wherein the first oxide semiconductor layer comprises first nanocrystals,
wherein the second oxide semiconductor layer comprises at least two crystals whose crystal axes are aligned,
wherein the two crystals in the second oxide semiconductor layer are c-axis-oriented in a direction substantially perpendicular to the upper surface of the second oxide semiconductor layer, and
wherein a length of one of the two crystals in the second oxide semiconductor layer in a c-axis direction is greater than or equal to five times a length of the one of the two crystals in the second oxide semiconductor layer in a direction of an a-axis or a b-axis.

7. The semiconductor device according to claim 6 ,
wherein the length of each of the two crystals in the second oxide semiconductor layer in the direction of the a-axis or the b-axis is greater than or equal to 2 nm and less than or equal to 50 nm.

8. The semiconductor device according to claim 6 ,
wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises In, Ga and Zn.

9. The semiconductor device according to claim 6 ,
wherein the gate insulating layer is a laminate film of silicon nitride and silicon oxynitride.

10. The semiconductor device according to claim 6 ,
wherein the oxide insulating layer comprises silicon oxide or aluminum oxide.

Assignees

• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei
• Sakakura Masayuki
• Watanabe Ryosuke
• Sakata Junichiro
• Akimoto Kengo
• Miyanaga Akiharu
• Hirohashi Takuya
• Kishida Hideyuki

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H01L21/2636

  Electricity · mapped topic

• H01L29/66969

  Electricity · mapped topic

• H01L29/04

  Electricity · mapped topic

• H01L29/12

  Electricity · mapped topic