Semiconductor device and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-2016307906-A1
Application number	US-201615196612-A
Country	US
Kind code	A1
Filing date	Jun 29, 2016
Priority date	Aug 30, 2012
Publication date	Oct 20, 2016
Grant date	—

Abstract

According to example embodiments, a semiconductor device may include a substrate having an upper surface defining a groove and an active region, a device isolation layer in the groove, and a contact structure on the active region. The device isolation exposes the active region and may have a top surface that is higher than a top surface of the active region. The contact structure may include a first portion filling a gap region delimited by a sidewall of the device isolation layer and the top surface of the active region, the contact structure may include and a second portion on the device isolation layer so the second portion overlaps with the device isolation layer in a plan view.

First claim

1 - 45 . (canceled)

46 . A semiconductor device comprising:
a substrate having a device isolation layer defining an active region; a first cell gate structure buried in the substrate and crossing the active region in a first direction, the first cell gate structure comprising a gate conductive layer and a capping layer on the gate conductive layer; and a first contact structure on the active region, wherein at least a portion of the first contact structure contacts the capping layer at a recessed portion of the capping layer.

47 . The semiconductor device of claim 46 , wherein the first contact structure partially overlaps the capping layer.

48 . The semiconductor device of claim 47 , wherein the first contact structure partially overlaps the gate conductive layer.

49 . The semiconductor device of claim 46 , wherein the recessed portion of the capping layer is recessed from a topmost surface of the capping layer.

50 . The semiconductor device of claim 46 , further comprising a second cell gate structure spaced apart from the first cell gate structure and crossing the active region in the first direction.

51 . The semiconductor device of claim 50 further comprising a conductive pattern on the active region between the first and second cell gate structures.

52 . The semiconductor device of claim 51 , further comprising a second contact structure,
wherein the first contact structure is on the active region at a first side of the first cell gate structure that is opposite to a side of the first cell gate structure facing the conductive pattern, and the second contact structure is on the active region at a first side of the second cell gate structure that is opposite to a side of the second cell gate structure facing the conductive pattern.

53 . The semiconductor device of claim 52 , wherein the other portion of the first contact structure contacts and overlaps the active region at the first side of the first cell gate structure.

54 . The semiconductor device of claim 51 , further comprising a conductive line on the conductive pattern in a second direction perpendicular to the first direction.

55 . The semiconductor device of claim 46 , further comprising a contact pad and a capacitor on the first contact structure.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Seongho

Classifications

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title

• H01L27/10885

  Electricity · mapped topic

• H01L27/10855

  Electricity · mapped topic

• H01L27/10814 Primary

  Electricity · mapped topic

• H01L27/10876

  Electricity · mapped topic