Managed NAND performance throttling

Patent metadata

Field	Value
Publication number	US-10418115-B2
Application number	US-201816023926-A
Country	US
Kind code	B2
Filing date	Jun 29, 2018
Priority date	Jul 7, 2017
Publication date	Sep 17, 2019
Grant date	Sep 17, 2019

Abstract

Apparatus and methods are disclosed, including a memory device or a memory controller configured to determine that a condition has occurred that indicates a performance throttling operation, implement a performance throttling responsive to the determined condition, responsive to implementing the performance throttling, set a performance throttling status indicator in an exception event status attribute, receive a command from a host device across a memory device interface, perform the command, prepare a response to the command, the response including a flag indicating that the performance throttling status indicator is set in the exception event status attribute, and send the response to the host device. Methods of operation are disclosed, as well as machine-readable medium and other embodiments.

First claim

What is claimed is:

1. A memory device comprising:
a non-volatile memory array;
a memory controller configured to perform the operations comprising:
determining that a condition has occurred that indicates a performance throttling operation;
implementing a performance throttling responsive to the determined condition;
responsive to implementing the performance throttling, setting a performance throttling status indicator in an exception event status attribute;
receiving a read or write command from a host device across a memory device interface;
performing the read or write command;
preparing a response to the read or write command, the response including a flag indicating that the performance throttling status indicator is set in the exception event status attribute; and

sending the response to the host device.

2. The memory device of claim 1 , wherein the response is formatted as a Universal Flash Storage Protocol Information Unit (UPIU) message.

3. The memory device of claim 1 , wherein the host device and the memory device communicate using a Universal Flash Storage family of standards.

4. The memory device of claim 1 , wherein the memory controller is further configured to perform the operations of:
setting a throttling status attribute to a value indicating the condition.

5. The memory device of claim 1 , wherein the operations of including the flag indicating that the performance throttling status indicator is set comprises determining that a control attribute has an indicator set corresponding to the performance throttling status indicator, the indicator in the control attribute set by the host.

6. The memory device of claim 1 , wherein the condition is a temperature reading of a temperature sensor of the memory device transgressing a threshold.

7. The memory device of claim 1 , wherein the performance throttling comprises: reducing a number of parallel accesses to memory cells of the memory device or reducing a speed at which the memory cells are accessed.

8. A method of performance throttling at a memory device, the method comprising:
determining that a condition has occurred that indicates a performance throttling operation;
implementing a performance throttling responsive to the determined condition;
responsive to implementing the performance throttling, setting a performance throttling status indicator in an exception event status attribute;
receiving a read or write command from a host device across a memory device interface;
performing the read or write command;
preparing a response to the read or write command, the response including a flag indicating that the performance throttling status indicator is set in the exception event status attribute; and
sending the response to the host device.

9. The method of claim 8 , wherein the response is formatted as a Universal Flash Storage Protocol Information Unit (UPIU) message.

10. The method of claim 8 , wherein the host device and the memory device communicate using a Universal Flash Storage family of standards.

11. The method of claim 8 , further comprising:
setting a throttling status attribute to a value indicating the condition.

12. The method of claim 8 , wherein including the flag indicating that the performance throttling status indicator is set comprises determining that a control attribute has an indicator set corresponding to the performance throttling status indicator, the indicator in the control attribute set by the host.

13. The method of claim 8 , wherein the condition is a temperature reading of a temperature sensor of the memory device transgressing a threshold.

14. The method of claim 8 , wherein the performance throttling comprises: reducing a number of parallel accesses to memory cells of the memory device or reducing a speed at which the memory cells are accessed.

15. A non-transitory machine-readable medium, storing instructions, which when executed by a memory device, causes the memory device to perform operations comprising:
determining that a condition has occurred that indicates a performance throttling operation;
implementing a performance throttling responsive to the determined condition;
responsive to implementing the performance throttling, setting a performance throttling status indicator in an exception event status attribute;
receiving a read or write command from a host device across a memory device interface; performing the read or write command;
preparing a response to the read or write command, the response including a flag indicating that the
performance throttling status indicator is set in the exception event status attribute; and
sending the response to the host device.

16. The machine-readable medium of claim 15 , wherein the response is formatted as a Universal Flash Storage Protocol Information Unit (UPIU) message.

17. The machine-readable medium of claim 15 , wherein the host device and the memory device communicate using a Universal Flash Storage family of standards.

18. The machine-readable medium of claim 15 , wherein the instructions further comprise:
setting a throttling status attribute to a value indicating the condition.

19. The machine-readable medium of claim 15 , wherein the operations of including the flag indicating that the performance throttling status indicator is set comprises determining that a control attribute has an indicator set corresponding to the performance throttling status indicator, the indicator in the control attribute set by the host.

20. The machine-readable medium of claim 15 , wherein the condition is a temperature reading of a temperature sensor of the memory device transgressing a threshold.

21. The machine-readable medium of claim 15 , wherein the performance throttling comprises:
reducing a number of parallel accesses to memory cells of the memory device or reducing a speed at which the memory cells are accessed.

Assignees

• Micron Technology Inc

Inventors

• Blodgett Greg A
• Jean Sebastien Andre

Classifications

• G06F12/1466 Primary

  Key-lock mechanism · CPC title

• G06F12/1458

  by checking the subject access rights · CPC title

• G06F12/1416

  by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights (G06F12/1458 takes precedence) · CPC title

• G06F3/0622

  in relation to access · CPC title

• G06F12/1441

  for a range · CPC title