Storage devices including dynamic internal thermal throttling

Patent metadata

Field	Value
Publication number	US-10175667-B2
Application number	US-201615098427-A
Country	US
Kind code	B2
Filing date	Apr 14, 2016
Priority date	Aug 17, 2015
Publication date	Jan 8, 2019
Grant date	Jan 8, 2019

Abstract

A storage device may include a nonvolatile memory including a plurality of memory blocks and a memory controller configured to determine a comparison between an idle current value of the nonvolatile memory and a reference current value and to adjust, based on the comparison, a start temperature at which the storage device begins operating speed control of the storage device.

First claim

What is claimed is:

1. A storage device comprising:
a nonvolatile memory including a plurality of memory blocks; and,
a memory controller configured to determine a comparison between an idle current value of the nonvolatile memory and a reference current value and to adjust, based on the comparison, a start temperature at which the storage device begins operating speed control of the storage device,
wherein the memory controller is further configured to increase the start temperature from a first value when the idle current value is greater than the reference current value.

2. The storage device of claim 1 , wherein the memory controller decreases the start temperature from the first value when the idle current value is smaller than the reference current value.

3. The storage device of claim 1 , wherein the memory controller receives a command that includes the idle current value from an external test device and stores the received idle current value in at least one memory block of the plurality of memory blocks.

4. The storage device of claim 3 , wherein the at least one memory block of the plurality of memory blocks is within a security area in which bad area information of the nonvolatile memory and the idle current value of the nonvolatile memory are stored.

5. The storage device of claim 1 , further comprising:
a temperature sensor configured to detect temperature and to output information of the detected temperature to the memory controller.

6. The storage device of claim 5 ,
wherein the storage device is configured to operate in a first mode in which the storage device operates at first speed that is lower than normal speed when the detected temperature is equal to or greater than a first start temperature and the detected temperature is included in a first temperature range that is lower than a second start temperature,
wherein the storage device is configured to operate in a second mode in which the storage device operates at second speed that is lower than the first speed when the detected temperature is equal to or greater than the second start temperature and the detected temperature is included in a second temperature range that is lower than a third start temperature, and
wherein the storage device is configured to operate in a third mode in which the storage device operates at third speed that is lower than the second speed when the detected temperature is included in a third temperature range that is greater than the third start temperature.

7. The storage device of claim 6 , wherein the memory controller includes a first reference current value corresponding to the first temperature range, a second reference current value corresponding to the second temperature range, and a third reference, current value corresponding to the third temperature range.

8. The storage device of claim 7 ,
wherein the memory controller increases the first start temperature from a first value when a first idle current value of the storage device corresponding to the first temperature range is greater than the first reference current value,
wherein the memory controller increases the second start temperature from a second value when a second idle current value of the storage device corresponding to the second temperature range is greater than the second reference current value, and
wherein the memory controller increases the third start temperature from a third value when a third idle current value of the storage device corresponding to the third temperature range is greater than the third reference current value.

9. The storage device of claim 7 ,
wherein the memory controller decreases the first start temperature from a first value when a first idle current value of the storage device corresponding to the first temperature range is less than the first reference current value,
wherein the memory controller decreases the second start temperature from a second value when a second idle current value of the storage device corresponding to the second temperature range is less, than the second reference current value, and
wherein the memory controller decreases the third start temperature from a third value when a third idle current value of the storage device corresponding to the third temperature range is less than the third reference current value.

10. The storage device of claim 1 , wherein the idle current value is stored in at least one memory block of the plurality of memory blocks or in a read only memory.

11. A storage device comprising:
a nonvolatile memory including a plurality of memory blocks;
a temperature sensor configured to detect a detected temperature; and
a memory controller configured to determine a comparison between an idle current value of the storage device and a reference current value and to adjust, based on the comparison, a start temperature at which the storage device begins operating speed control of the storage device,
wherein the memory controller is configured to operate at an operating speed lower than an operating speed of a normal operation when the detected temperature obtained from the temperature sensor is equal to or greater than the start temperature,
wherein the memory controller is further configured to receive the idle current value via a command, and
wherein the command is a combination of one or more normal commands or a vendor unit command.

12. The storage device of claim 11 ,
wherein the nonvolatile memory comprises cell strings arranged on a substrate, and
wherein ones of the cell strings comprise at least one selection transistor and memory cells stacked on the substrate in a direction perpendicular to the substrate.

13. The storage device of claim 12 , wherein ones of the at least one selection transistor and the memory cells are charge-trap-type transistors.

14. A storage device comprising:
a nonvolatile memory; and
a memory controller coupled to the nonvolatile memory,
wherein the memory controller is configured to:
determine an idle current value of the storage device corresponding to a current flowing to the storage device when the storage device performs no read, erase, and/or program operation;
determine a comparison between the idle current value of the storage device and a reference current value;
adjust a start temperature based on the comparison between the idle current value of the storage device and the reference current value;
determine a comparison between a present temperature of the storage device and the start temperature; and
regulate a speed of the storage device based on the comparison between the present temperature of the storage device and the start temperature.

15. The storage device of claim 14 ,
wherein the memory controller is configured to, adjust the start temperature by increasing the start temperature when the idle current value is greater than the reference current value, and
wherein the memory controller is configured to regulate the speed of the storage device by operating the storage device at a first speed when the present temperature of the storage device is less than the start temperature and operating the storage device at a second speed that is less than the first speed when the present temperature of the storage device is greater than the start temperature.

16. The storage device of claim 14 ,
wherein the memory controller is configured to adjust the start temperature by decreasing the start temperature when the idle current value is less than the reference current value, and
wherein the memory controller is configured to regulate the speed of the storage device by operating

Assignees

• Samsung Electronics Co Ltd

Inventors

• Bang Kwangkyu
• Kang Heeyoub
• Bang Hyojae
• Lee Kitaek

Classifications

• G06F3/0616

  in relation to life time, e.g. increasing Mean Time Between Failures [MTBF] · CPC title

• G06F1/206

  comprising thermal management · CPC title

• G06F3/0659 Primary

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G05B15/02 Primary

  electric · CPC title

• G06F3/0673

  Single storage device · CPC title