Multi-multidimensional computer architecture for big data applications

US10417005B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10417005-B2
Application numberUS-201715700488-A
CountryUS
Kind codeB2
Filing dateSep 11, 2017
Priority dateMar 17, 2015
Publication dateSep 17, 2019
Grant dateSep 17, 2019

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A data processing apparatus is provided comprising a front-end interface electronically coupled to a main processor. The front-end interface is configured to receive data stored in a repository, in particular an external storage and/or a network, determine whether the data is a single-access data or a multiple-access data by analyzing an access parameter designating the data, route the multiple-access data for processing by the main processor, and route the single-access data for pre-processing by the front-end interface and routing results of the pre-processing to the main processor.

First claim

Opening claim text (preview).

The invention claimed is: 1. A data processing apparatus, comprising: a front-end interface electronically coupled to a main processor; the front-end interface is configured to: receive input data from a data repository, wherein the data repository includes one of an external storage device and/or a network repository accessible using a network interface; determine whether the input data is a single-access data or a multiple-access data by analyzing an access parameter designating the input data; route the multiple-access data for processing by the main processor; and route the single-access data for pre-processing by the front-end interface and routing results of the pre-processing to the main processor. 2. The data processing apparatus of claim 1 , wherein the access parameter is based on a reception time between two receptions of a same data on the front-end interface, or a request time between two requests of a same data by the main processor. 3. The data processing apparatus of claim 2 , wherein the access parameter is measured as a relative time between two receptions and/or two request of a same data on the front-end interface. 4. The data processing apparatus of claim 2 , wherein the access parameter is measured as an absolute time of a second access of a same data on the front-end interface. 5. The data processing apparatus of claim 2 , wherein the access parameter is measured by counting a number of data accesses between two accesses of a same data on the front-end interface. 6. The data processing apparatus of claim 2 , wherein the single access data is determined by comparing the access parameter to a threshold value. 7. The data processing apparatus of claim 1 , wherein the front-end interface comprises at least one local processor adapted to: access a local memory unit; pre-process the single-access data and/or store the single-access data to the local memory unit; and route results of the pre-processing to the main processor for further processing. 8. The data processing apparatus of claim 1 , wherein the pre-processing comprises a group of application specific instructions for filtering and aggregating a plurality of data elements of the single-access data. 9. The data processing apparatus of claim 8 , wherein the at least one local processor of the front-end interface incorporates a pre-processing instruction transfer module, wherein the pre-processing instruction transfer module is configured to receive the group of application specific instructions from the main processor, convert the group of application specific instructions to a machine language of the at least one processor, and execute the machine language on the at least one processor to perform the pre-processing. 10. The data processing apparatus of claim 1 , wherein the front-end interface comprises a temporary memory unit for storing at least some members of the results before routed to the main processor. 11. The data processing apparatus of claim 10 , wherein memory storage addressed in the temporary memory unit is mapped into storage addresses of a main memory of the main processor. 12. The data processing apparatus of claim 1 , wherein the front-end interface is adapted to receive a main processor output from the main processor and to use the main processor output to pre-process the single-access data. 13. The data processing apparatus of claim 1 , wherein a local processor instruction is generated by a device driver incorporated into an operating system configured to operate the main processor to perform the pre-processing. 14. A method, comprising: receiving input data stored in a repository, wherein the data repository includes one of an external storage device and/or a network repository accessible using a network interface; determining whether the input data is a single-access data or a multiple-access data by analyzing an access parameter designating the data; routing the multiple-access data for processing by a main processor; and routing the single-access data for pre-processing by a front-end interface and routing results of the pre-processing to the main processor. 15. A non-transitory computer readable media storing computer instructions, that when executed by one or more processors, cause the one or more processors to perform the steps of: receive input data stored in a repository, wherein the data repository includes one of an external storage device and/or a network repository accessible using a network interface; determine whether the input data is a single-access data or a multiple-access data by analyzing an access parameter designating the data; route the multiple-access data for processing by a main processor; and route the single-access data for pre-processing by a front-end interface and routing results of the pre-processing to the main processor.

Assignees

Inventors

Classifications

  • G06F9/5027Primary

    the resource being a machine, e.g. CPUs, Servers, Terminals · CPC title

  • G06F9/3895Primary

    for complex operations, e.g. multidimensional or interleaved address generators, macros · CPC title

  • Techniques for rebalancing the load in a distributed system · CPC title

  • using an input/output type connection, e.g. channel, I/O port · CPC title

  • considering software capabilities, i.e. software resources associated or available to the machine · CPC title

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Frequently asked questions

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What does patent US10417005B2 cover?
A data processing apparatus is provided comprising a front-end interface electronically coupled to a main processor. The front-end interface is configured to receive data stored in a repository, in particular an external storage and/or a network, determine whether the data is a single-access data or a multiple-access data by analyzing an access parameter designating the data, route the multiple…
Who is the assignee on this patent?
Huawei Tech Co Ltd
What technology area does this patent fall under?
Primary CPC classification G06F9/5027. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Sep 17 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).