Chopper-stabilized amplifier with analog-driven level shifter

Patent metadata

Field	Value
Publication number	US-10411664-B2
Application number	US-201816042006-A
Country	US
Kind code	B2
Filing date	Jul 23, 2018
Priority date	Dec 29, 2017
Publication date	Sep 10, 2019
Grant date	Sep 10, 2019

Abstract

A chopper-stabilized amplifier that includes an analog driven level shifter is disclosed. The analog driven level shifter changes the levels of a pair of complementary clock signals according to a level associated with an input signal to the chopper-stabilized amplifier. The level shifted complementary clock signals are used to control switching devices used for chopping input signals of various voltages. The chopper-stabilized amplifier also includes symmetrical passive RC notch filters having two cut-off frequencies to reduce ripple noise from the chopping.

First claim

The invention claimed is:

1. A chopper-stabilized amplifier comprising:
a first chopper circuit that chops an input signal at a chopping frequency using at least one switching device controlled by a pair of complementary clock signals that are level shifted;
an amplifier coupled to an output of the first chopper circuit that amplifies the chopped input signal;
a second chopper circuit coupled to an output of the amplifier that chops the amplified and chopped input signal at the chopping frequency using at least one switching device controlled by a pair of complementary clock signals that are not level shifted;
symmetrical RC notch filters coupled to an output of the second chopper circuit that filter signals from the second chopper circuit and output an output signal; and
an analog-driven level shifter circuit that receives the input signal and, based on a voltage level of the input signal, level shifts the pair of complementary clock signals that are not level shifted to produce the pair of complementary clock signals that are level shifted.

2. The chopper-stabilized amplifier according to claim 1 , wherein the amplifier is an operational transconductance amplifier.

3. The chopper-stabilized amplifier according to claim 1 , wherein the symmetrical RC notch filters include a first notch filter that has a cutoff frequency at a third harmonic of the chopping frequency or at a fifth harmonic of the chopping frequency and a second notch filter that has a cutoff frequency at a first harmonic of the chopping frequency.

4. The chopper stabilized amplifier according to claim 1 , wherein the analog-driven level shifter operates at supply voltages between a lower voltage of 4 volts and an upper voltage of greater than or equal to 12 volts.

5. The chopper stabilized amplifier according to claim 1 , wherein the analog-driven level shifter includes an operational amplifier having a built in offset and configured as a voltage follower, the operational amplifier receiving the input signal and outputting a virtual ground for the pair of complementary clock signals that are level shifted.

6. The chopper stabilized amplifier according to claim 5 , wherein the analog-driven level shifter comprises a stack of diode-connected transistors connected between a positive supply voltage of the analog-driven level shifter and an output of the operational amplifier to set an amplitude of the pair of complementary clock signals that are level shifted, the amplitude above the virtual ground.

7. The chopper stabilized amplifier according to claim 5 , wherein the analog-driven level shifter comprises at least one capacitor that capacitively couples the pair of complementary clock signals that are not level shifted to the output of the operational amplifier to produce the pair of complementary clock signals that are level shifted.

8. A system comprising:
an analog-driven level shifter circuit that receives an input signal and, based on a voltage level of the input signal, level shifts a pair of complementary clock signals;
a first chopper circuit that chops the input signal at a chopping frequency using at least one switching device controlled by the level shifted pair of complementary clock signals;
an amplifier coupled to an output of the first chopper circuit that amplifies the chopped input signal; and
a second chopper circuit coupled to an output of the amplifier that chops the amplified chopped input signal at the chopping frequency using at least one switching device controlled by the pair of complementary clock signals.

9. The system according to claim 8 , wherein the amplifier is an operational transconductance amplifier.

10. The system according to claim 8 , wherein the analog-driven level shifter operates at supply voltages between a lower voltage of 4 volts and an upper voltage of greater than or equal to 12 volts.

11. The system according to claim 8 , wherein the analog-driven level shifter includes an operational amplifier having a built in offset and configured as a voltage follower, the operational amplifier receiving the input signal and outputting a virtual ground for the pair of complementary clock signals that are level shifted.

12. The system according to claim 11 , wherein the analog-driven level shifter comprises a stack of diode-connected transistors connected between a positive supply voltage of the analog-driven level shifter and an output of the operational amplifier to set an amplitude of the pair of complementary clock signals that are level shifted, the amplitude above the virtual ground.

13. The system according to claim 11 , wherein the analog-driven level shifter comprises capacitors that capacitively couple the pair of complementary clock signals that are not level shifted to the output of the operational amplifier to produce the pair of complementary clock signals that are level shifted.

14. The system according to claim 8 , further comprising:
a first symmetrical RC notch filter and a second symmetrical RC notch filter, wherein the first symmetrical RC notch filter is configured to receive a differential signal from the second chopper circuit and the second symmetrical RC notch filter is configured to received a differential signal from the first symmetrical RC notch filter.

15. The system according to claim 14 , wherein the first symmetrical RC notch filter has a cutoff frequency at a third harmonic of the chopping frequency or at a fifth harmonic of the chopping frequency and the second symmetrical RC notch filter that has a cutoff frequency at a first harmonic of the chopping frequency.

16. A method for amplifying a signal, the method comprising:
receiving a differential input signal that has a common-mode voltage level that is greater than a pair of complementary clock signals;
level-shifting, using an analog-driven level shifter, the pair of complementary clock signals according to the voltage level of the differential input signal;
chopping the differential input signal by switching its polarity using at least one switching device of a first chopping circuit that are controlled by the level shifted pair of complementary clock signals;
amplifying the chopped differential input signal; and
chopping the amplified chopped differential input signal by switching its polarity using at least one switching device of a second chopping circuit that are controlled by a pair of complementary clock signals with no level shift.

17. The method according to claim 16 , wherein the analog-driven level shifter includes an operational amplifier having a built in offset and configured as a voltage follower, the operational amplifier receiving the differential input signal and outputting a virtual ground for the pair of complementary clock signals that are level shifted.

18. The method according to claim 17 , wherein the analog-driven level shifter comprises a stack of diode-connected transistors connected between a positive supply voltage of the analog-driven level shifter and an output of the operational amplifier to set an amplitude of the pair of complementary clock signals that are level shifted, the amplitude above the virtual ground.

19. The method according to claim 18 , wherein the analog-driven level shifter comprises capacitors that capacitively couple the pair of complementary clock signals that are not level shifted to the output of the operational amplifier to produce the pair of complementary clock signals that are level shifted.

20. The method according to claim 16 , further comprising:
filtering the output of

Assignees

• Semiconductor Components Ind Llc

Inventors

• Stanescu Cornel D
• Puscasu Razvan

Classifications

• H03F2200/408

  the output amplifying stage of an amplifier comprising three power stages · CPC title

• H03F3/50

  Amplifiers in which input is applied to, or output is derived from, an impedance common to input and output circuits of the amplifying element, e.g. cathode follower · CPC title

• H03F3/387

  with semiconductor devices only · CPC title

• H03F2200/372

  Noise reduction and elimination in amplifier · CPC title

• H03F2200/271

  the DC-isolation amplifier, e.g. chopper amplifier, modulation/demodulation amplifier, uses capacitive isolation means, e.g. capacitors · CPC title