Process for creating a high density magnetic tunnel junction array test platform

Patent metadata

Field	Value
Publication number	US-10411185-B1
Application number	US-201815992815-A
Country	US
Kind code	B1
Filing date	May 30, 2018
Priority date	May 30, 2018
Publication date	Sep 10, 2019
Grant date	Sep 10, 2019

Abstract

A method for a photo and/or electron beam lithographic fabricating processes for producing a pillar array test device. The method includes receiving a wafer having a plurality of bit cells arranged in a grid and etching a plurality of bottom electrode traces to connect a plurality of bottom electrode pads in a centrally located bit cell to each of the bit cells in the grid. The method further includes fabricating an array of magnetic tunnel junction pillars onto each respective pad in the centrally located bit cell. The wafer is then planarized. The method further includes etching a plurality of top electrode traces to connect the plurality of magnetic tunnel junction pillars to each of the bit cells in the grid, and outputting the wafer for subsequent testing.

First claim

What is claimed is:

1. A method for an electron beam lithographic fabricating process for producing a pillar array test device, the method, comprising:
receiving a wafer having a plurality of bit cells arranged in a grid;
etching a plurality of bottom electrode traces to connect a plurality of bottom electrode pads in a centrally located bit cell to each of the bit cells in the grid;
fabricating an array of magnetic tunnel junction pillars onto each respective pad in the centrally located bit cell;
planarizing the wafer;
etching a plurality of top electrode traces to connect the plurality of magnetic tunnel junction pillars to each of the bit cells in the grid; and
outputting the wafer for subsequent testing.

2. The method of claim 1 , wherein the plurality of top electrode traces connect to the bit cells in the grid using vias.

3. The method of claim 1 , further comprising fabricating an array of metal posts on top of the plurality of bottom electrode pads to function as a base for the array of magnetic tunnel junction pillars.

4. The method of claim 1 , wherein each of the plurality of bottom electrode traces comprises tantalum nitride.

5. The method of claim 4 , wherein each of the plurality of top electrode traces comprises tantalum nitride.

6. The method of claim 1 , wherein each of the plurality of bit cells further comprises a CMOS driving transistor for individually addressing each of the magnetic tunnel junction pillars.

7. The method of claim 1 , further comprising depositing a silicon oxide passivation layer on the surface of the surface of the wafer.

8. A method for a fabricating process for producing a pillar array test device, the method, comprising:
receiving a wafer having a plurality of bit cells arranged in a grid having a first density wherein each of the plurality of bit cells further comprises a CMOS driving transistor;
etching a plurality of bottom electrode traces to connect a plurality of bottom electrode pads in a centrally located bit cell to each of the bit cells in the grid;
fabricating an array of magnetic tunnel junction pillars onto each respective pad in the centrally located bit cell and having a second density higher than the first density;
planarizing the wafer;
etching a plurality of top electrode traces to connect the plurality of magnetic tunnel junction pillars to each of the bit cells in the grid; and
outputting the wafer for subsequent testing.

9. The method of claim 8 , wherein the plurality of top electrode traces connect to the bit cells in the grid using vias.

10. The method of claim 8 , wherein an array of metal posts are fabricated on top of the plurality of bottom electrode pads to function as a base for the array of magnetic tunnel junction pillars.

11. The method of claim 8 , wherein each of the plurality of bottom electrode traces comprises tantalum nitride.

12. The method of claim 8 , wherein each of the plurality of top electrode traces comprises tantalum nitride.

13. The method of claim 8 , wherein each of the CMOS driving transistors are for individually addressing each of the magnetic tunnel junction pillars.

14. The method of claim 8 , wherein a silicon oxide passivation layer is deposited on the surface of the surface of the wafer.

15. A method for a fabricating process for producing a pillar array test device, the method, comprising:
receiving a wafer having a plurality of bit cells arranged in a grid having a first density wherein each of the plurality of bit cells further comprises a CMOS driving transistor;
etching a plurality of bottom electrode traces to connect a plurality of bottom electrode pads in a centrally located bit cell to each of the bit cells in the grid;
fabricating an array of magnetic tunnel junction pillars onto each respective pad in the centrally located bit cell and having a second density higher than the first density;
planarizing the wafer;
etching a plurality of top electrode traces to connect the plurality of magnetic tunnel junction pillars to each of the bit cells in the grid, wherein the plurality of top electrode traces connect to the bit cells in the grid using vias; and
outputting the wafer for subsequent testing.

16. The method of claim 8 , wherein an array of metal posts are fabricated on top of the plurality of bottom electrode pads to function as a base for the array of magnetic tunnel junction pillars.

17. The method of claim 8 , wherein each of the plurality of bottom electrode traces comprises tantalum nitride.

18. The method of claim 8 , wherein each of the plurality of top electrode traces comprises tantalum nitride.

19. The method of claim 8 , wherein each of the CMOS driving transistors are for individually addressing each of the magnetic tunnel junction pillars.

20. The method of claim 8 , wherein a silicon oxide passivation layer is deposited on the surface of the surface of the wafer.

Assignees

• Spin Transfer Tech Inc
• Spin Memory Inc

Inventors

• Manandhar Pradeep
• Shrivastava Prachi
• Pinarbasi Mustafa
• Boone Thomas

Classifications

• H10P95/06

  Planarisation of inorganic insulating materials · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H01L21/3065

  Electricity · mapped topic

• H01L27/222

  Electricity · mapped topic

• H01L21/31051

  Electricity · mapped topic