System and method for depletion mode and enhancement mode transistors

Patent metadata

Field	Value
Publication number	US-10411008-B2
Application number	US-201815938922-A
Country	US
Kind code	B2
Filing date	Mar 28, 2018
Priority date	Oct 15, 2015
Publication date	Sep 10, 2019
Grant date	Sep 10, 2019

Abstract

Circuits and devices for bidirectional normally-off switches are described. A circuit for a bidirectional normally-off switch includes a depletion mode transistor and an enhancement mode transistor. The depletion mode transistor includes a first source/drain node, a second source/drain node, a first gate, and a second gate. The enhancement mode transistor includes a third source/drain node and a fourth source/drain node, and a third gate. The third source/drain node is coupled to the first source/drain node.

First claim

What is claimed is:

1. A circuit comprising a first input/output node and a second input/output node, the circuit comprising:
a depletion mode transistor comprising a first source/drain node, a second source/drain node, a first gate, and a second gate, wherein the first gate is coupled to a first control node and the second gate is coupled to a second control node;
a first enhancement mode transistor comprising a first silicon substrate, a third source/drain node and a fourth source/drain node, a first body, and a third gate, wherein the third source/drain node is coupled to the first source/drain node, and wherein the fourth source/drain node is coupled to the first body and the first input/output node different from the first control node and the second control node; and
a second enhancement mode transistor comprising a fifth source/drain node and a sixth source/drain node, a second body, and a fourth gate, wherein the fifth source/drain node is coupled to the second source/drain node, and wherein the sixth source/drain node is coupled to the second body and the second input/output node different from the first control node and the second control node.

2. The circuit of claim 1 , wherein the depletion mode transistor, the first enhancement mode transistor, and the second enhancement mode transistor are disposed on the same semiconductor substrate.

3. The circuit of claim 1 , further comprising a first diode coupled between the first gate and the first input/output node.

4. The circuit of claim 1 , further comprising a first Schottky diode coupled between the third source/drain node and the fourth source/drain node.

5. The circuit of claim 1 , further comprising a second diode coupled between the second gate and the second input/output node.

6. The circuit of claim 1 , wherein the first, the second, the third, and the fourth gates are coupled to different control nodes that are configured to be independently controlled.

7. The circuit of claim 6 , wherein the third gate and the first gate are coupled to separate control nodes of a first controller, and wherein the fourth gate and the second gate are coupled to separate control nodes of a second controller.

8. The circuit of claim 7 , wherein the first controller and the second controller are part of an integrated controller.

9. The circuit of claim 1 , wherein the first enhancement mode transistor comprises a p-type field effect transistor.

10. The circuit of claim 1 , wherein the depletion mode transistor is a high electron mobility transistor.

11. The circuit of claim 1 , wherein the first enhancement mode transistor comprises an n-type silicon field effect transistor or a normally off III-V transistor.

12. A semiconductor device comprising:
a normally-on transistor comprising a first source/drain node, a second source/drain node, a first gate, and a second gate isolated from the first gate;
a first normally-off transistor comprising a third source/drain node and a fourth source/drain node, a first body, and a third gate, wherein the third source/drain node is coupled to the first source/drain node, and wherein the fourth source/drain node is directly coupled to the first body; and
a second normally-off transistor comprising a fifth source/drain node and a sixth source/drain node, a second body, and a fourth gate, wherein the fifth source/drain node is coupled to the second source/drain node, and wherein the sixth source/drain node is directly coupled to the second body.

13. The semiconductor device of claim 12 , wherein the first, the second, the third, and the fourth gates are coupled to different potential nodes that are independently controlled.

14. The semiconductor device of claim 13 , wherein the third gate and the first gate are coupled to separate potential nodes of a first controller, and wherein the fourth gate and the second gate are coupled to separate potential nodes of a second controller.

15. The semiconductor device of claim 12 , wherein the fourth source/drain node is coupled to a first side potential node, and wherein the sixth source/drain node is coupled to a second side potential node.

16. The semiconductor device of claim 15 , further comprising a first diode coupled between the first gate and the first side potential node and a second diode coupled between the second gate and the second side potential node.

17. The semiconductor device of claim 15 , wherein the first normally-off transistor and the second normally-off transistor comprise p-type field effect transistors.

18. The semiconductor device of claim 12 , wherein each of the first normally-off transistor and the second normally-off transistor comprises an n-type field effect transistor.

19. The semiconductor device of claim 12 , wherein the normally-on transistor is disposed in or over a first substrate, and wherein the first normally-off transistor is disposed in or over a second substrate different from the first substrate.

20. The semiconductor device of claim 12 , wherein the normally-on transistor and the first normally-off transistor are disposed in or over a same substrate.

21. A circuit comprising:
a depletion mode transistor comprising a first source/drain node, a second source/drain node, a first gate, and a second gate, wherein the depletion mode transistor is a normally-on transistor;
a first enhancement mode transistor comprising a third source/drain node and a fourth source/drain node, and a third gate, wherein the third source/drain node is coupled to the first source/drain node; and
a second enhancement mode transistor comprising a fifth source/drain node and a sixth source/drain node, and a fourth gate, wherein the fifth source/drain node is coupled to the second source/drain node, and wherein the circuit is configured to operate in
a first mode in which the depletion mode transistor is in a high resistance state, the first enhancement mode transistor is in a low resistance state, and the second enhancement mode transistor is in a high resistance state,
a second mode in which the depletion mode transistor is in a low resistance state of the depletion mode transistor, the first enhancement mode transistor is in the low resistance state of the first enhancement mode transistor, and the second enhancement mode transistor is in a low resistance state of the second enhancement mode transistor, and
a third mode in which the depletion mode transistor is in the high resistance state of the depletion mode transistor, the first enhancement mode transistor is in the low resistance state of the first enhancement mode transistor, and the second enhancement mode transistor is in the low resistance state of the second enhancement mode transistor.

22. The circuit of claim 21 , wherein the fourth source/drain node is coupled to a first side potential node.

23. The circuit of claim 22 , further comprising a first diode coupled between the first gate and the first side potential node.

24. The circuit of claim 23 , wherein the first enhancement mode transistor comprises a p-type field effect transistor.

25. The circuit of claim 21 , wherein the first enhancement mode transistor comprises an n-type silicon field effect transistor or a normally off III-V transistor.

26. The circuit of claim 21 , further comprising a first Schottky diode coupled between the third source/drain node and the fourth source/drain node.

27. The circuit of claim 21 , wh

Assignees

• Infineon Technologies Austria Ag

Inventors

• Prechtl Gerhard
• Zojer Bernhard

Classifications

• H03K2017/6875

  using self-conductive, depletion FETs · CPC title

• H03K17/687 Primary

  the devices being field-effect transistors · CPC title

• H03K2217/0054

  Gating switches, e.g. pass gates · CPC title

• H01L27/0629 Primary

  Electricity · mapped topic

• H01L27/0694

  Electricity · mapped topic