Bidirectional normally-off III-V high electron mobility transistor (HEMT)devices and circuits

Patent metadata

Field	Value
Publication number	US-9960157-B2
Application number	US-201514884388-A
Country	US
Kind code	B2
Filing date	Oct 15, 2015
Priority date	Oct 15, 2015
Publication date	May 1, 2018
Grant date	May 1, 2018

Abstract

Circuits and devices for bidirectional normally-off switches are described. A circuit for a bidirectional normally-off switch includes a depletion mode transistor and an enhancement mode transistor. The depletion mode transistor includes a first source/drain node, a second source/drain node, a first gate, and a second gate. The enhancement mode transistor includes a third source/drain node and a fourth source/drain node, and a third gate. The third source/drain node is coupled to the first source/drain node.

First claim

What is claimed is:

1. A semiconductor device comprising:
a bidirectional III-V high electron mobility transistor (HEMT) comprising a first source/drain node, a second source/drain node, a first gate, and a second gate isolated from the first gate, wherein the first gate is coupled to a first control node and the second gate is coupled to a second control node;
a first field effect transistor (FET) comprising a first silicon substrate, a third source/drain node and a fourth source/drain node, and a third gate, wherein the third source/drain node is coupled to the first source/drain node, wherein the fourth source/drain node is coupled to a input/output node different from the first control node and the second control node; and
a second FET comprising a second silicon substrate, a fifth source/drain node and a sixth source/node, and a fourth gate, wherein the fifth source/drain node is coupled to the second source/drain node.

2. The device of claim 1 , wherein the first, the second, the third, and the fourth gates are coupled to different potential nodes that are independently controlled.

3. The device of claim 1 , wherein the first silicon substrate and the second silicon substrate are a same substrate.

4. The device of claim 1 , wherein the III-V HEMT is formed on the same substrate.

5. The device of claim 1 , wherein the III-V HEMT is a GaN device comprising a AlGaN/GaN material stack.

6. The device of claim 1 , wherein the first FET and the second FET comprise silicon FETs or GaN MOSFETs.

7. The device of claim 1 , wherein the III-V HEMT device is a depletion mode device.

8. The device of claim 1 , wherein the III-V HEMT device is a normally ON device.

9. A circuit comprising:
a high electron mobility transistor comprising a first source/drain node, a second source/drain node, a first gate, and a second gate, wherein the high electron mobility transistor is a depletion mode transistor;
a first enhancement mode transistor comprising a third source/drain node and a fourth source/drain node, and a third gate, wherein the third source/drain node is coupled to the first source/drain node; and
a second enhancement mode transistor comprising a fifth source/drain node and a sixth source/drain node, and a fourth gate, wherein the fifth source/drain node is coupled to the second source/drain node, wherein the circuit is configured to operate in
a first mode in which the high electron mobility transistor is in a high resistance state, the first enhancement mode transistor is in a low resistance state, the second enhancement mode transistor is in a high resistance state,
a second mode in which the high electron mobility transistor is in a low resistance state of the high electron mobility transistor, the first enhancement mode transistor is in the low resistance state of the first enhancement mode transistor, the second enhancement mode transistor is in a low resistance state of the second enhancement mode transistor, and
a third mode in which the high electron mobility transistor is in the high resistance state of the high electron mobility transistor, the first enhancement mode transistor is in the low resistance state of the first enhancement mode transistor, the second enhancement mode transistor is in the low resistance state of the second enhancement mode transistor.

10. The circuit of claim 9 , wherein the fourth source/drain node is coupled to a first side potential node.

11. The circuit of claim 10 , further comprising a first diode coupled between the first gate and the first side potential node.

12. The circuit of claim 11 , wherein the first enhancement mode transistor comprises a p-type field effect transistor.

13. The circuit of claim 9 , wherein the first enhancement mode transistor comprises an n-type silicon field effect transistor or a normally off III-V transistor.

14. The circuit of claim 9 , further comprising a first Schottky diode coupled between the third source/drain node and the fourth source/drain node.

15. The circuit of claim 9 , further comprising:
a second enhancement mode transistor comprising a fifth source/drain node and a sixth source/drain node, and a fourth gate, wherein the fifth source/drain node is coupled to the second source/drain node.

16. The circuit of claim 15 , wherein the sixth source/drain node is coupled to a second potential node, the circuit further comprising a second diode coupled between the second gate and a second potential node.

17. The circuit of claim 15 , wherein the first, the second, the third, and the fourth gates are coupled to different potential nodes that are configured to be independently controlled.

18. The circuit of claim 17 , wherein the third gate and the first gate are coupled to separate potential nodes of a first controller, and wherein the fourth gate and the second gate are coupled to separate potential nodes of a second controller.

19. The circuit of claim 18 , wherein the first controller and the second controller are part of an integrated controller.

20. A semiconductor device comprising:
a bidirectional high electron mobility transistor comprising a first source/drain node, a second source/drain node, a first gate, and a second gate isolated from the first gate, wherein the high electron mobility transistor is a normally on transistor;
a first normally-off transistor comprising a third source/drain node and a fourth source/drain node, a first body, and a third gate, wherein the third source/drain node is coupled to the first source/drain node, wherein the fourth source/drain node is directly connected to the first body; and
a second normally-off transistor comprising a fifth source/drain node and a sixth source/drain node, a second body, and a fourth gate, wherein the fifth source/drain node is coupled to the second source/drain node, wherein the sixth source/drain node is directly connected to the second body.

21. The semiconductor device of claim 20 , wherein the first, the second, the third, and the fourth gates are coupled to different potential nodes that are independently controlled.

22. The semiconductor device of claim 21 , wherein the third gate and the first gate are coupled to separate potential nodes of a first controller, and wherein the fourth gate and the second gate are coupled to separate potential nodes of a second controller.

23. The semiconductor device of claim 20 , wherein the fourth source/drain node is coupled to a first side potential node, wherein the sixth source/drain node is coupled to a second side potential node.

24. The semiconductor device of claim 23 , further comprising a first diode coupled between the first gate and the first side potential node and a second diode coupled between the second gate and the second side potential node.

25. The semiconductor device of claim 23 , wherein the first normally-off transistor and the second normally-off transistor comprise p-type field effect transistors.

26. The semiconductor device of claim 20 , wherein each of the first normally-off transistor and the second normally-off transistor comprises an n-type field effect transistor.

27. The semiconductor device of claim 20 , wherein the high electron mobility transistor is disposed in or over a first substrate, wherein the first normally-off transistor is disposed in or over a second substrate different from the first substrate.

28. The semiconductor device

Assignees

• Infineon Technologies Austria Ag

Inventors

• Prechtl Gerhard
• Zojer Bernhard

Classifications

• H03K2217/0054

  Gating switches, e.g. pass gates · CPC title

• H03K17/687 Primary

  the devices being field-effect transistors · CPC title

• H03K2017/6875

  using self-conductive, depletion FETs · CPC title

• H01L27/0694

  Electricity · mapped topic

• H01L27/0883

  Electricity · mapped topic