Memory modules, memory systems including the same and methods of operating memory systems

Patent metadata

Field	Value
Publication number	US-10404286-B2
Application number	US-201715664295-A
Country	US
Kind code	B2
Filing date	Jul 31, 2017
Priority date	Nov 30, 2016
Publication date	Sep 3, 2019
Grant date	Sep 3, 2019

Abstract

A memory module includes data memories and at least one parity memory. Each of the data memories includes a first memory cell array with a first memory region to store data set corresponding to a plurality of burst lengths and a second memory region to store first parity bits to perform error detection/correction associated with the data set. The at least one parity memory includes a second memory cell array with a first parity region to store parity bits associated with user data set corresponding to all of the data set stored in each of the data memories and a second parity region to store second parity bits for error detection/correction associated with the parity bits.

First claim

What is claimed is:

1. A memory module, comprising:
a plurality of data memories to store a user data including a plurality of data sets, each data set corresponding to a plurality of burst lengths; and
at least one parity memory to store a plurality of parity bits being generated based on the user data, wherein:
each of the plurality of data memories includes a first memory cell array that includes a first memory region to store each data set and a second memory region to store first parity bits for performing first error detection/correction of each data set,
the at least one parity memory includes a second memory cell array that includes a first parity region to store the plurality of parity bits for performing second error detection/correction of the user data and a second parity region to store second parity bits for performing third error detection/correction of the plurality of parity bits.

2. The memory module as claimed in claim 1 , wherein:
the first parity bits are to detect an error in one or more of the plurality of data memories, and
the parity bits are to correct the error detected in the one or more of the plurality of data memories.

3. The memory module as claimed in claim 2 , wherein the error in the one or more plurality of data memories is:
a transmission error which occurs while each data set is transmitted to each of the plurality of data memories, or
a storage error which occurs while each data set is stored in each of the plurality of data memories.

4. The memory module as claimed in claim 1 , wherein each of the plurality of data memories includes:
a cyclic redundancy check (CRC) checker to calculate data check bits based on each data set, compare the data check bits and the first parity bits, and selectively store each data set in the first memory region based on a result of the comparison.

5. The memory module as claimed in claim 4 , wherein the CRC checker is to:
transmit an alert signal to a memory controller when at least one of corresponding bits of the data check bits or the first parity bits are not equal based on the result of the comparison, and
receive each data set and the first parity bits from the memory controller again.

6. The memory module as claimed in claim 1 , wherein each of the plurality of data memories includes:
an error correction code (ECC) engine that includes a cyclic redundancy check (CRC) checker, the CRC checker to calculate data check bits based on each data set, compare the data check bits and the first parity bits, and selectively store each data set in the first memory region based on a result of the comparison.

7. The memory module as claimed in claim 6 , wherein the ECC engine includes:
an ECC decoder to correct an error of a data set read from the first memory region based on the first parity bits read from the second memory region in a read operation of the plurality of data memories.

8. The memory module as claimed in claim 7 , wherein the CRC checker and the ECC decoder are to use a same error correction code.

9. The memory module as claimed in claim 1 , wherein:
each of the first memory cell array and the second memory cell array includes a plurality of dynamic memory cells or a plurality of resistive type memory cells,
each of the first memory cell array and the second memory cell array includes a three-dimensional memory cell array, and
the memory module includes a dual in-line memory module (DIMM).

10. A memory system, comprising:
a memory module including a plurality of data memories and at least one parity memory; and
a memory controller to control the memory module, wherein:
each of the plurality of data memories includes a first memory cell array that includes a first memory region to store data set corresponding to a plurality of burst lengths and a second memory region to store first parity bits to perform error detection/correction, associated with the data set,
the at least one parity memory includes a second memory cell array that includes a first parity region to store parity bits associated with user data set corresponding to all of the data set stored in each of the plurality of data memories and a second parity region to store second parity bits for error detection/correction, associated with the parity bits, and
the memory controller includes:
a cyclic redundancy check (CRC) generator to generate the first parity bits based on each of the data set and to generate the second parity bits based on the parity bits; and
a parity generator to generate the parity bits based on the user data set.

11. The memory controller as claimed in claim 10 , wherein the memory controller includes:
a CRC/parity checker to detect an error in one or more of the plurality of data memories based on the first parity bits read from each of the plurality of data memories and correct the detected error in the one or more of the plurality of data memories based on the parity bits read from the parity memory in a read operation of the plurality of data memories.

12. The memory system as claimed in claim 11 , wherein the memory controller is to control data of the one or more of the plurality of data memories in which the error is detected.

13. The memory system as claimed in claim 10 , wherein each of the data memories includes:
a CRC checker to calculate data check bits based on the data set, compare the data check bits and the first parity bits, and selectively store the data set in the first memory region based on a result of the comparison.

14. The memory system as claimed in claim 13 , wherein the CRC checker is to:
transmit an alert signal to the memory controller when at least one of corresponding bits of the data check bits or the first parity bits are not equal based on the result of the comparison and receive the data set and the first parity bits from the memory controller again.

15. The memory system as claimed in claim 10 , wherein each of the plurality of data memories includes:
an error correction code (ECC) engine that includes a CRC checker to calculate data check bits based on the data set, compare the data check bits and the first parity bits, and selectively store the data set in the first memory region based on a result of the comparison.

16. The memory system as claimed in claim 15 , wherein the ECC engine includes an ECC decoder to correct an error of a data set read from the first memory region using the first parity bits read from the second memory region in a read operation of the data memory.

17. The memory system as claimed in claim 15 , wherein the ECC engine is to use a single error correction (SEC) code or a single error correction/double error detection (SECDED) code.

18. A memory module, comprising:
a first data memory;
a second data memory; and
at least one parity memory, wherein:
each of the first data memory and the second data memory includes a first memory region to store a data set corresponding to a plurality of burst lengths and a second memory region to store first parity bits for the data set,
the at least one parity memory includes a first parity region to store parity bits corresponding to a user data set and a second parity region to store second parity bits for the parity bits, wherein
each of the first data memory and the second data memory includes a cyclic redundancy check (CRC) checker to calculate data check bits based on the data set, compare the data check bits and the first parity bits, and selectively store the data set in the first memory region based on the comparison.

19. The me

Assignees

• Samsung Electronics Co Ltd

Inventors

• Sin Hoon
• Cha Sang-Uhn
• Ryu Ye-Sin
• Cho Seong-Jin

Classifications

• G11C29/04

  Detection or location of defective memory elements {, e.g. cell constructio details, timing of test signals} · CPC title

• G06F11/1076

  Parity data used in redundant arrays of independent storages, e.g. in RAID systems · CPC title

• G06F11/1012 Primary

  using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence) · CPC title

• G11C2029/0411

  Online error correction · CPC title

• H03M13/13

  Linear codes · CPC title