Tiered ecc single-chip and double-chip chipkill scheme

Patent metadata

Field	Value
Publication number	US-2016011940-A1
Application number	US-201514606334-A
Country	US
Kind code	A1
Filing date	Jan 27, 2015
Priority date	Jul 10, 2014
Publication date	Jan 14, 2016
Grant date	—

Abstract

Exemplary embodiments provide a tiered error correction code (ECC) Chipkill system, comprising: a device ECC incorporated into at least a portion of a plurality of memory devices that corrects n-bit memory device-level failures in the respective memory device, and transmits a memory device failure signal when any memory device-level failure is greater than n-bits and beyond correction capability of the device ECC device; and a system-level ECC device external to the plurality of memory devices is responsive to receiving the memory device failure signal to correct the memory device failure based on a system ECC parity.

First claim

We claim:

1 . A tiered error correction code (ECC) system, comprising:
a device ECC incorporated into at least a portion of a plurality of memory devices that corrects n-bit memory device-level failures in the respective memory device, and transmits a memory device failure signal when any memory device-level failure is greater than n-bits and beyond correction capability of the device ECC device; and a system-level ECC device external to the plurality of memory devices that is responsive to receiving the memory device failure signal to correct the memory device failure based on a system ECC parity.

2 . The system of claim 1 , wherein the tiered ECC system corrects a single memory device failure and detects any number of device failures and their locations within a memory module.

3 . The system of claim 1 , wherein the tiered ECC system comprise:
a memory device-level comprising the plurality of memory chips within a memory module, each associated with a respective device ECC engine and an ECC parity; and a system-level comprising the system-level ECC engine and the system ECC device parity.

4 . The system of claim 3 , wherein each of the at least a portion of the memory devices transmits the ECC failure signal using an additional data-bus burst or an extra pin, such that receipt of a particular memory device failure signal automatically informs the system ECC engine of an identity of the transmitting memory device and a location of the error.

5 . The system of claim 3 , wherein the ECC parity associated with the memory devices comprises a row parity chip.

6 . The system of claim 5 , wherein the row parity chip provides the memory devices with n-bit correction capability and is used to correct single chip failures, where n equals one or two.

7 . The system of claim 1 , wherein the memory device failure signal is integrated into a data-bus cyclic redundancy check (CRC) data.

8 . The system of claim 7 , wherein the memory device failure signal comprises 1 bit, the CRC data comprises 7 bits, and a burst length of the data-bus is increased to 10.

9 . The system of claim 1 , further including an additional diagonal parity chip to extend the single-chip correction of the single-chip Chipkill system to a tiered ECC double-chip Chipkill system that performs double-chip correction plus an ability to detect any number of failures in the memory devices comprising a memory module.

10 . The system of claim 9 , wherein when there are two memory device failures and two corresponding memory device failure signals, and wherein the system ECC engine uses the diagonal parity chip and a row parity chip alternatively to recover data from the failed memory devices.

11 . The system of claim 10 , wherein responsive to the system ECC engine receiving more than two memory device failure signals, the system ECC engine determines which ones of the memory devices failed and the number of memory devices that failed based on the memory device failure signals and sends an uncorrectable error signal to a memory controller.

12 . A method of providing a tiered ECC system, the ECC system including a plurality of memory devices, comprising:
incorporating a device ECC in at least a portion of each of the plurality of memory devices that corrects n-bit memory device-level failures in the respective memory device, and transmits a memory device failure signal when any memory device-level failure is greater than n-bits and beyond correction capability of the device ECC device; and using a system-level ECC device external to the plurality of memory devices that is responsive to receiving the memory device failure signal to correct the memory device failure based on a system ECC parity.

13 . The method of claim 13 , further comprising: using the tiered ECC system to correct a single memory device failure and to detect any number of device failures and their locations within a memory module.

14 . The method of claim 13 , further comprising:
incorporating the plurality of memory chips within a memory module into a memory device-level, each associated with a respective device ECC engine and an ECC parity; and incorporating the system-level ECC engine and the system ECC device parity into a system-level.

15 . The method of claim 12 , wherein each of the at least a portion of the memory devices transmits the ECC failure signal using an additional data-bus burst or an extra pin, such that receipt of a particular memory device failure signal automatically informs the system ECC engine of an identity of the transmitting memory device and a location of the error.

16 . The method of claim 12 , wherein the ECC parity associated with the memory devices comprises a row parity chip.

17 . The method of claim 16 , wherein the row parity chip provides the memory devices with n bit correction capability and is used to correct single chip failures, where n equals one or two.

18 . The method of claim 13 , further comprising: integrating the memory device failure signal into a data-bus cyclic redundancy check (CRC) data.

19 . The method of claim 12 , wherein the memory device failure signal comprises 1 bit, the CRC data comprises 7 bits, and a burst length of the data-bus is increased to 10.

20 . The method of claim 13 , further comprising: providing the memory module with an additional diagonal parity chip to extend the single-chip correction of the single-chip Chipkill system to a tiered ECC double-chip Chipkill system that performs double-chip correction plus an ability to detect any number of failures in the memory devices comprising a memory module.

21 . The method of claim 20 , wherein when there are two memory device failures and two corresponding memory device failure signals, the system ECC engine uses the diagonal parity chip and a row parity chip alternatively to recover data from the failed memory devices.

22 . The method of claim 21 , wherein responsive to the system ECC engine receiving more than two memory device failure signals, determining by the system ECC engine which ones of the memory devices failed and the number of memory devices that failed based on the memory device failure signals and sends an uncorrectable error signal to a memory controller.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hu Chaohong
• Kang Uksong
• Zheng Hongzhong

Classifications

• G06F11/108 Primary

  Parity data distribution in semiconductor storages, e.g. in SSD · CPC title

• G06F11/1076 Primary

  Parity data used in redundant arrays of independent storages, e.g. in RAID systems · CPC title

• G06F11/1012

  using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence) · CPC title

• G06F2211/1057

  Parity-multiple bits-RAID6, i.e. RAID 6 implementations · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title