Integrated circuit having a multiplying injection-locked oscillator

Patent metadata

Field	Value
Publication number	US-10404262-B2
Application number	US-201615390362-A
Country	US
Kind code	B2
Filing date	Dec 23, 2016
Priority date	May 2, 2011
Publication date	Sep 3, 2019
Grant date	Sep 3, 2019

Abstract

Methods and apparatuses featuring a multiplying injection-locked oscillator are described. Some embodiments include a pulse-generator-and-injector and one or more injection-locked oscillators. The outputs of the pulse-generator-and-injector can be injected into corresponding injection points of an injection-locked oscillator. In embodiments that include multiple injection-locked oscillators, the outputs of each injection-locked oscillator can be injected into the corresponding injection points of the next injection-locked oscillator. Some embodiments reduce deterministic jitter by dynamically modifying the loop length of an injection-locked oscillator, and/or by using a duty cycle corrector, and/or by multiplexing/blending the outputs from multiple delay elements of an injection-locked oscillator.

First claim

What is claimed is:

1. A circuit, comprising:
a pulse-generator-and-injector (PGAI) circuit having a PGAI input to receive a reference clock signal and a set of PGAI outputs to output a set of injection signals, wherein each injection signal in the set of injection signals is a delayed version of a sequence of pulses;
a set of injection-locked oscillators (ILOs) having a set of injection inputs and a set of ILO outputs, wherein each injection input in the set of injection inputs is coupled to a respective PGAI output in the set of PGAI outputs; and
a multiplexer/blender (MUX/B) having a set of MUX/B inputs, a MUX/B output, and a MUX/B select input, wherein each ILO output in the set of ILO outputs is coupled with a respective MUX/B input in the set of MUX/B inputs, and wherein a PGAI output is coupled with the MUX/B select input.

2. The circuit of claim 1 , wherein the PGAI circuit comprises a pulse generator (PG) circuit to generate the sequence of pulses.

3. The circuit of claim 2 , wherein the PGAI circuit comprises a chain of delay elements to generate multiple delayed versions of the sequence of pulses.

4. The circuit of claim 2 , wherein the sequence of pulses includes return-to-null pulses.

5. The circuit of claim 2 , wherein the PG circuit comprises:
a first PG circuit to generate a first sequence of pulses based on a reference signal; and
a second PG circuit to generate the sequence of pulses based on the first sequence of pulses.

6. The circuit of claim 1 , wherein the set of ILOs includes a single ILO.

7. The circuit of claim 1 , wherein the set of ILOs includes multiple ILOs configured in a sequence so that outputs of a given ILO in the sequence are provided as injection signals to a next ILO in the sequence.

8. A memory controller circuit that controls an operation of a memory device, comprising:
a pulse-generator-and-injector (PGAI) circuit having a PGAI input to receive a reference clock signal and a set of PGAI outputs to output a set of injection signals, wherein each injection signal in the set of injection signals is a delayed version of a sequence of pulses;
a set of injection-locked oscillators (ILOs) having a set of injection inputs and a set of ILO outputs, wherein each injection input in the set of injection inputs is coupled to a respective PGAI output in the set of PGAI outputs;
a multiplexer/blender (MUX/B) having a set of MUX/B inputs, a MUX/B output, and a MUX/B select input, wherein each ILO output in the set of ILO outputs is coupled with a respective MUX/B input in the set of MUX/B inputs, and wherein a PGAI output is coupled with the MUX/B select input; and
an output pin, coupled to the MUX/B output, to provide a clock signal to the memory device.

9. The memory controller circuit of claim 8 , wherein the PGAI circuit comprises a pulse generator (PG) circuit to generate the sequence of pulses.

10. The memory controller circuit of claim 9 , wherein the PGAI circuit comprises a chain of delay elements to generate multiple delayed versions of the sequence of pulses.

11. The memory controller circuit of claim 9 , wherein the sequence of pulses includes return-to-null pulses.

12. The memory controller circuit of claim 9 , wherein the PG circuit comprises:
a first PG circuit to generate a first sequence of pulses based on a reference signal; and
a second PG circuit to generate the sequence of pulses based on the first sequence of pulses.

13. The memory controller circuit of claim 8 , wherein the set of ILOs includes a single ILO.

14. The memory controller circuit of claim 8 , wherein the set of ILOs includes multiple ILOs configured in a sequence so that outputs of a given ILO in the sequence are provided as injection signals to a next ILO in the sequence.

15. A memory system, comprising:
a memory circuit having a memory clock input; and
a memory controller circuit that controls an operation of the memory circuit, comprising:
a pulse-generator-and-injector (PGAI) circuit having a PGAI input to receive a reference clock signal and a set of PGAI outputs to output a set of injection signals, wherein each injection signal in the set of injection signals is a delayed version of a sequence of pulses;
a set of injection-locked oscillators (ILOs) having a set of injection inputs and a set of ILO outputs, wherein each injection input in the set of injection inputs is coupled to a respective PGAI output in the set of PGAI outputs; and
a multiplexer/blender (MUX/B) having a set of MUX/B inputs, a MUX/B output, and a MUX/B select input, wherein each ILO output in the set of ILO outputs is coupled with a respective MUX/B input in the set of MUX/B inputs, wherein a PGAI output is coupled with the MUX/B select input, and wherein the MUX/B output is coupled with the memory clock input.

16. The memory system of claim 15 , wherein the PGAI circuit comprises:
a pulse generator (PG) circuit to generate the sequence of pulses; and
a chain of delay elements to generate multiple delayed versions of the sequence of pulses.

17. The memory system of claim 16 , wherein the sequence of pulses includes return-to-null pulses.

18. The memory system of claim 16 , wherein the PG circuit comprises:
a first PG circuit to generate a first sequence of pulses based on a reference signal; and
a second PG circuit to generate the sequence of pulses based on the first sequence of pulses.

19. The memory system of claim 15 , wherein the set of ILOs includes a single ILO.

20. The memory system of claim 15 , wherein the set of ILOs includes multiple ILOs configured in a sequence so that outputs of a given ILO in the sequence are provided as injection signals to a next ILO in the sequence.

Assignees

• Rambus Inc

Inventors

• Zerbe Jared L
• Daly Barry W
• Dunwell Dustin T
• Carusone Anthony C
• Eble Iii John C

Classifications

• H03K3/0315

  Ring oscillators · CPC title

• H03L7/24 Primary

  using a reference signal directly applied to the generator · CPC title

• H03K3/0322

  with differential cells · CPC title

• H03K5/133

  using a chain of active delay devices · CPC title

• H03K5/1565

  the output pulses having a constant duty cycle · CPC title