Integrated circuit having a multiplying injection-locked oscillator

Patent metadata

Field	Value
Publication number	US-9564911-B2
Application number	US-201514858830-A
Country	US
Kind code	B2
Filing date	Sep 18, 2015
Priority date	May 2, 2011
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

Methods and apparatuses featuring a multiplying injection-locked oscillator are described. Some embodiments include a pulse-generator-and-injector and one or more injection-locked oscillators. The outputs of the pulse-generator-and-injector can be injected into corresponding injection points of an injection-locked oscillator. In embodiments that include multiple injection-locked oscillators, the outputs of each injection-locked oscillator can be injected into the corresponding injection points of the next injection-locked oscillator. Some embodiments reduce deterministic jitter by dynamically modifying the loop length of an injection-locked oscillator, and/or by using a duty cycle corrector, and/or by multiplexing/blending the outputs from multiple delay elements of an injection-locked oscillator.

First claim

What is claimed is:

1. An injection-locked oscillator, comprising:
a set of sub-ring stages configured in a loop, each sub-ring stage including a chain of delay elements and a sub-ring multiplexer/blender, at least one delay element configured to receive an injection signal, and at least two delay elements configured to provide input signals to the sub-ring multiplexer/blender; and
a multiplexer to receive an output signal from each sub-ring multiplexer/blender in each sub-ring stage, and to output an output signal of the injection-locked oscillator.

2. The injection-locked oscillator of claim 1 , wherein the injection signal is a sequence of pulses.

3. The injection-locked oscillator of claim 2 , wherein the sequence of pulses includes return-to-null pulses.

4. The injection-locked oscillator of claim 1 , wherein the injection signal is a periodic signal having deterministic jitter.

5. A memory controller circuit that controls an operation of a memory device, comprising:
an injection-locked oscillator comprising:
a set of sub-ring stages configured in a loop, each sub-ring stage including a chain of delay elements and a sub-ring multiplexer/blender, at least one delay element configured to receive an injection signal, and at least two delay elements configured to provide input signals to the sub-ring multiplexer/blender; and
a multiplexer to receive an output signal from each sub-ring multiplexer/blender in each sub-ring stage, and to output an output signal of the injection-locked oscillator; and

an output pin to provide a clock signal to the memory device, wherein the clock signal is generated based on the output signal of the injection-locked oscillator.

6. The memory controller circuit of claim 5 , wherein the injection signal is a sequence of pulses.

7. The memory controller circuit of claim 6 , wherein the sequence of pulses includes return-to-null pulses.

8. memory controller circuit of claim 5 , wherein the injection signal is a periodic signal having deterministic jitter.

9. The memory controller circuit of claim 5 , further comprising a duty cycle corrector (DCC) to adjust pulse widths of the output signal of the injection-locked oscillator so that the width of the narrowest pulse in the deterministic jitter pattern is substantially equal to the width of the second narrowest pulse in the deterministic jitter pattern.

10. A method, comprising:
receiving a set of three or more pulse-width values corresponding to a deterministic jitter pattern in an output signal of a duty cycle corrector (DCC); and
in response to determining that the minimum pulse-width value in the set of three or more pulse-width values is not substantially equal to another pulse-width value in the set of three or more pulse-width values, adjusting a control input value of the DCC to increase the minimum pulse-width value in the set of three or more pulse-width values.

11. The method of claim 10 , further comprising, in response to determining that the minimum pulse-width value in the set of three or more pulse-width values is substantially equal to another pulse-width value in the set of three or more pulse-width values, storing the control input value of the DCC.

12. The method of claim 10 , further comprising receiving, at the DCC, the output signal having the deterministic jitter pattern from an injection-locked oscillator having a set of injection points, wherein each injection point is capable of receiving an input signal in a set of input signals.

13. The method of claim 10 , further comprising adjusting, by the DCC, pulse widths of the output signal based on the control input value of the DCC.

Assignees

• Rambus Inc

Inventors

• Zerbe Jared L
• Daly Barry W
• Dunwell Dustin T
• Carusone Anthony Chan
• Eble Iii John C

Classifications

• H03L7/24 Primary

  using a reference signal directly applied to the generator · CPC title

• H03K3/0322

  with differential cells · CPC title

• H03K5/133

  using a chain of active delay devices · CPC title

• H03K5/1565

  the output pulses having a constant duty cycle · CPC title

• H03K3/0315

  Ring oscillators · CPC title