Soft start systems and methods for multi-stage step-up converters

Patent metadata

Field	Value
Publication number	US-9608512-B2
Application number	US-201414211922-A
Country	US
Kind code	B2
Filing date	Mar 14, 2014
Priority date	Mar 15, 2013
Publication date	Mar 28, 2017
Grant date	Mar 28, 2017

Abstract

A control circuit for a step-up converter includes a soft start module configured to control states of N transistor pairs of the step-up converter, where N is an integer greater than two. A driver module is in communication with the soft start module and configured to generate a first signal when N transistor pairs of the step-up converter are ready to switch. A first charging circuit is configured to charge (N−1) capacitors of the step-up converter to an input voltage of the step-up converter in response to the first signal and to generate a second signal when charging is complete. A second charging circuit is configured to sequentially charge the (N−1) capacitors of the step-up converter to (N−1) predetermined voltage values in response to the first signal and the second signal and before operation of the step-up converter begins.

First claim

What is claimed is:

1. A control circuit for a step-up converter, comprising:
a soft start module configured to control states of N transistor pairs of the step-up converter, where N is an integer greater than two;
a driver module in communication with the soft start module and configured to generate a first signal when N transistor pairs of the step-up converter are ready to switch;
a first charging circuit configured to charge (N−1) capacitors of the step-up converter to an input voltage of the step-up converter in response to the first signal and to generate a second signal when charging is complete; and
a second charging circuit configured to sequentially charge the (N−1) capacitors of the step-up converter to (N−1) predetermined voltage values in response to the first signal and the second signal and before operation of the step-up converter begins.

2. The control circuit of claim 1 , wherein the (N−1) predetermined voltage values correspond to (N−1) fractions, respectively, of an output voltage of the step-up converter.

3. The control circuit of claim 1 , wherein the second charging circuit is configured to charge the (N−1) capacitors ratiometrically before operation of the step-up converter.

4. The control circuit of claim 1 , wherein the second charging circuit is configured to charge the (N−1) capacitors to voltages that are ratios of an output voltage of the step-up converter.

5. The control circuit of claim 4 , wherein the ratios increase monotonically from a lowest ratio on an inner capacitor of the (N−1) capacitors to a highest ratio on an outer capacitor of the (N−1) capacitors.

6. The control circuit of claim 1 , wherein the second charging circuit is configured to sequentially:
charge the first one of the (N−1) capacitors to 1/N of an output voltage of the step-up converter;
charge a second one of the (N−1) capacitors to 2/N of the output voltage of the step-up converter; and
charge an (N−1) th one of the (N−1) capacitors to (N−1)/N of the output voltage of the step-up converter.

7. The control circuit of claim 6 , wherein the second charging circuit is configured to sequentially charge the (N−1) capacitors to (N−1) fractions of the output voltage, respectively, before operation.

8. The control circuit of claim 1 , wherein the second charging circuit charges an (N−1)th one of the (N−1) capacitors to (N−1)/N of an output voltage of the step-up converter.

9. The control circuit of claim 1 , wherein the first charging circuit includes a current charging circuit that pulls terminals of the (N−1) capacitors low.

10. A system comprising:
the control circuit of claim 1 ;
the step-up converter, wherein the step-up converter comprises:
an inductor including one end in communication with an input voltage supply;
the N transistor pairs, where N is an integer greater than one, wherein first and second transistors of a first pair of the N transistor pairs are connected together and communicate with the inductor, and
wherein third and fourth transistors of a second pair of the N transistor pairs are connected to the first and second transistors, respectively;
the (N−1) capacitors connected between the N transistor pairs, respectively;
an output capacitor in communication with at least one transistor of the N transistor pairs; and
a control module to control states of the N transistor pairs during operation of the step-up converter.

11. A step-up converter circuit comprising:
an inductor including one end in communication with an input voltage supply;
N transistor pairs connected in series, where N is an integer greater than one, wherein first and second transistors of a first pair of the N transistor pairs are connected together at a node, and wherein the node is in communication with another terminal of the inductor, and
wherein third and fourth transistors of a second pair of the N transistor pairs are connected to the first and second transistors, respectively;
(N−1) capacitors having terminals connected between the N transistor pairs, respectively; and
an output capacitor having a terminal in communication with at least one transistor of the N th transistor pair;
a control module to initiate converter operation after the (N−1) capacitors are charged to (N−1) predetermined voltage values and to control states of the N transistor pairs during converter operation; and
a first charging circuit configured to initially charge the (N−1) capacitors to the input voltage before charging to the (N−1) predetermined voltage values.

12. The step-up converter circuit of claim 11 , further comprising a soft start module configured to charge the (N−1) capacitors to the (N−1) predetermined voltage values.

13. The step-up converter circuit of claim 11 , wherein the (N−1) predetermined voltage values correspond to (N−1) predetermined ratios of an output voltage of the step-up converter.

14. The step-up converter circuit of claim 13 , wherein when N is greater than two, the (N−1) predetermined ratios increase monotonically from a lowest ratio on an inner capacitor of the (N−1) capacitors to a highest ratio on an outer capacitor of the (N−1) capacitors.

15. A step-up converter circuit comprising:
an inductor including one end in communication with an input voltage supply;
N transistor pairs connected in series, where N is an integer greater than one, wherein first and second transistors of a first pair of the N transistor pairs are connected together at a node, and wherein the node is in communication with another terminal of the inductor, and
wherein third and fourth transistors of a second pair of the N transistor pairs are connected to the first and second transistors, respectively;
(N−1) capacitors having terminals connected between the N transistor pairs, respectively; and
an output capacitor having a terminal in communication with at least one transistor of the N th transistor pair;
a control module to initiate converter operation after the (N−1) capacitors are charged to (N−1) predetermined voltage values and to control states of the N transistor pairs during converter operation; and
a soft start module configured to sequentially:
charge a first one of the (N−1) capacitors to 1/N of an output voltage of the step-up converter;
charge a second one of the (N−1) capacitors to 2/N of the output voltage of the step-up converter; and
charge an (N−1) th one of the (N−1) capacitors to (N−1)/N of the output voltage of the step-up converter.

16. A step-up converter circuit comprising:
an inductor including one end in communication with an input voltage supply;
N transistor pairs connected in series, where N is an integer greater than one, wherein first and second transistors of a first pair of the N transistor pairs are connected together at a node, and wherein the node is in communication with another terminal of the inductor, and
wherein third and fourth transistors of a second pair of the N transistor pairs are connected to the first and second transistors, respectively;
(N−1) capacitors having terminals connected between the N transistor pairs, respectively; and
an output capacitor having a terminal in communication with at least one transistor of the N th transistor pair;
a control module to initiate converter operation after the (N−1) capacitors are charged to (N−1) predetermined voltage values and to control states of the N transistor pairs during converter operation; and
a start-up circuit including:
a soft start module configured to control states of the N transistor pairs;
a driver module in communication with the soft start module and configured to

Assignees

• Maxim Integrated Products

Inventors

• Zhak Serhii Mikhailovich
• Belch Mark Anthony
• Miwa Brett A
• Harrington David
• King Jonathan

Classifications

• H02M3/158

  including plural semiconductor devices as final control devices for a single load · CPC title

• H02M1/36 Primary

  Means for starting or stopping converters · CPC title

• H02M3/07

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• H02M3/1584

  with a plurality of power processing stages connected in parallel · CPC title

• H02M1/14

  Arrangements for reducing ripples from DC input or output · CPC title