Distributed switches to suppress transient electrical overstress-induced latch-up

Patent metadata

Field	Value
Publication number	US-10404059-B2
Application number	US-201715428535-A
Country	US
Kind code	B2
Filing date	Feb 9, 2017
Priority date	Feb 9, 2017
Publication date	Sep 3, 2019
Grant date	Sep 3, 2019

Abstract

Distributed switches to suppress transient electrical overstress-induced latch-up are provided. In certain configurations, an integrated circuit (IC) or semiconductor chip includes a transient electrical overstress detection circuit that activates a transient overstress detection signal in response to detecting a transient electrical overstress event between a pair of power rails. The IC further includes mixed-signal circuits and latch-up suppression switches distributed across the IC, and the latch-up suppression switches temporarily clamp the power rails to one another in response to activation of the transient overstress detection signal to inhibit latch-up of the mixed-signal circuits.

First claim

What is claimed is:

1. An integrated circuit with distributed latch-up suppression, the integrated circuit comprising:
a first power rail;
a second power rail;
a first electrical overstress detection circuit configured to activate a first transient overstress detection signal in response to detecting a transient electrical overstress event between the first power rail and the second power rail;
a first driver circuit configured to buffer the first transient overstress detection signal to generate a first pair of trigger signals including a first trigger signal and a second trigger signal that are logically inverted relative to one another;
a plurality of complementary metal oxide semiconductor (CMOS) circuits powered by the first power rail and the second power rail and distributed across the integrated circuit; and
a first plurality of thyristors electrically connected between the first power rail and the second power rail, wherein when the integrated circuit is powered, the first plurality of thyristors are operable to clamp the first power rail and the second power rail in response to activation of the first pair of trigger signals so as to inhibit latch-up of the plurality of CMOS circuits, and to release in response to deactivation of the first pair of trigger signals.

2. The integrated circuit of claim 1 wherein a first thyristor of the first plurality of thyristors comprises an NPN bipolar transistor and a PNP bipolar transistor that are cross-coupled, wherein a base of the PNP bipolar transistor is configured to receive the first trigger signal and a base of the NPN bipolar transistor is configured to receive the second trigger signal.

3. The integrated circuit of claim 1 , further comprising a power clamp electrically connected between the first power rail and the second power rail and operable to turn on in response to activation of the second trigger signal.

4. The integrated circuit of claim 1 , wherein the first electrical overstress detection circuit comprises a detection capacitor and a detection resistor electrically connected in series between the first power rail and the second power rail.

5. The integrated circuit of claim 2 , wherein the first thyristor operates with a first activation voltage and a first holding voltage when the first pair of trigger signals are deactivated, and with a second activation voltage and a second holding voltage when the first pair of trigger signals are activated.

6. The integrated circuit of claim 5 , wherein the first activation voltage and the first holding voltage are greater than a nominal voltage difference between the first power rail and the second power rail, and wherein the second activation voltage and the second holding voltage are less than the nominal voltage difference.

7. The integrated circuit of claim 2 , wherein the first thyristor comprises a P+ anode region serving as an emitter of the PNP bipolar transistor, an N+ cathode region serving as an emitter of the NPN bipolar transistor, an N+ trigger region configured to receive the first trigger signal, and a P+ trigger region configured to receive the second trigger signal.

8. The integrated circuit of claim 7 , wherein the N+ trigger region and the P+ trigger region are positioned between the P+ anode region and the N+ cathode region.

9. The integrated circuit of claim 8 , wherein the first thyristor further comprises a first gate structure between P+ anode region and the N+ trigger region, and a second gate structure between N+ anode region and the P+ trigger region.

10. The integrated circuit of claim 7 , wherein the first thyristor further comprises a diode having an anode electrically connected to the emitter of the NPN bipolar transistor and a cathode electrically connected to the emitter of the PNP bipolar transistor.

11. The integrated circuit of claim 3 , wherein the power clamp comprises an n-type metal oxide semiconductor (NMOS) clamp transistor having a drain electrically connected to the first power rail, a source electrically connected to the second power rail, and a gate configured to receive the second trigger signal.

12. The integrated circuit of claim 1 , further comprising a second electrical overstress detection circuit configured to activate a second transient overstress detection signal in response to detecting the transient electrical overstress event, a second driver circuit configured to buffer the second transient overstress detection signal to generate a second pair of trigger signals, and a second plurality of thyristors electrically connected between the first power rail and the second power rail and controlled by the second pair of trigger signals.

13. A method of inhibiting latch-up in an integrated circuit, the method comprising:
powering a mixed-signal circuit using a first power rail and a second power rail;
activating a transient overstress detection signal in response to detecting a transient electrical overstress event between the first power rail and the second power rail;
buffering the transient overstress detection signal to generate a pair of trigger signals including a first trigger signal and a second trigger signal that are logically inverted relative to one another;
clamping the first power rail and the second power rail by turning on a plurality of thyristors in response to activation of the pair of trigger signals to thereby inhibit latch-up in the mixed-signal circuit; and
releasing the plurality of thyristors in response to deactivation of the pair of trigger signals.

14. The method of claim 13 , further comprising operating the plurality of thyristors with a first activation voltage and a first holding voltage when the pair of trigger signals are deactivated, and with a second activation voltage and a second holding voltage when the pair of trigger signals are activated.

15. The method of claim 14 , wherein the first activation voltage and the first holding voltage are greater than a nominal voltage difference between the first power rail and the second power rail, and wherein the second activation voltage and the second holding voltage are less than the nominal voltage difference.

16. An interface for a semiconductor chip, the interface comprising:
a first interface pad;
a second interface pad;
an electrical overstress detection circuit configured to activate a transient overstress detection signal in response to detecting a transient electrical overstress event between the first interface pad and the second interface pad;
a driver circuit configured to buffer the transient overstress detection signal to generate a pair of trigger signals including a first trigger signal and a second trigger signal that are logically inverted relative to one another;
a mixed-signal circuit configured to receive power from the first interface pad and the second interface pad; and
a plurality of thyristors electrically connected between the first interface pad the second interface pad, wherein the plurality of thyristors are operable to clamp the first interface pad and the second interface pad in response to activation of the pair of trigger signals to inhibit latch-up of the mixed-signal circuit, and to release in response to deactivation of the pair of trigger signals.

17. The interface of claim 16 , wherein a first thyristor of the plurality of thyristors comprises an NPN bipolar transistor and a PNP bipolar transistor that are cross-coupled, wherein a base of the PNP bipolar transistor is configured to receive the first trigger signal and a base of the NPN bipolar transistor is configured to receive the second trigge

Assignees

• Analog Devices Inc

Inventors

• Salcedo Javier Alejandro
• Parthasarathy Srivatsan
• He Linfeng
• Zhou Yuanzhong

Classifications

• H10W20/427 Primary

  Power or ground buses · CPC title

• H02H7/205 Primary

  for controlled semi-conductors which are not included in a specific circuit arrangement · CPC title

• H01L27/0262

  Electricity · mapped topic

• H01L27/0248

  Electricity · mapped topic

• H01L23/5286

  Electricity · mapped topic