Apparatus for transceiver signal isolation and voltage clamp

Patent metadata

Field	Value
Publication number	US-9275991-B2
Application number	US-201313766541-A
Country	US
Kind code	B2
Filing date	Feb 13, 2013
Priority date	Feb 13, 2013
Publication date	Mar 1, 2016
Grant date	Mar 1, 2016

Abstract

An apparatus for transceiver signal isolation and voltage clamp from transient electrical events includes a bi-directional protection device comprising a bipolar PNPNP device assembly, a first parasitic PNPN device assembly, and a second parasitic PNPN device assembly. The bipolar PNPNP device assembly includes an NPN bi-directional bipolar transistor, a first PNP bipolar transistor, and a second PNP bipolar transistor, and is configured to receive a transient voltage signal through first and second pads. The first and second pads are electrically connected to the PNPNP device assembly through emitters of the first and second PNP bipolar transistors. The bipolar PNPNP device assembly is electrically connected to a first parasitic PNPN device assembly comprising a parasitic PNP bipolar transistor and a first parasitic NPN bipolar transistor. The bipolar PNPNP device assembly is further connected to a second parasitic parasitic PNPN device assembly comprising the parasitic PNP bipolar transistor and a second parasitic NPN bipolar transistor. The base of the parasitic PNP bipolar transistor is connected to the substrate of the transceiver through a resistor to prevent triggering and breakdown of the first and second parasitic PNPN device assemblies.

First claim

What is claimed is:

1. An apparatus comprising:
a p-type substrate;
a first n-type well region, a second n-type well region, and a first p-type well region configured to form an NPN bi-directional transistor formed in the p-type substrate;
a first p-type active region disposed in the first n-type well region and a second p-type active region disposed in the second n-type well region;
a p-type tub surrounding the NPN bi-directional transistor and in physical contact with the first n-type well region, the second n-type well region and the first p-type well region;
an n-type tub surrounding the p-type tub;
a p-type epitaxial region surrounding the n-type tub;
wherein the first n-type well region, the p-type tub, and the n-type tub are configured to form a first parasitic NPN bipolar transistor; and
wherein the p-type epitaxial region, the n-type tub, and the p-type tub are configured to form a parasitic PNP bipolar transistor.

2. The apparatus of claim 1 , wherein the p-type epitaxial region is configured to form an emitter of the parasitic PNP bipolar transistor, and wherein the n-type tub is configured to form a base of the parasitic PNP bipolar transistor.

3. The apparatus of claim 2 , wherein the emitter and the base of the parasitic PNP bipolar transistor are connected through a first resistor formed in the p-type epitaxial region.

4. The apparatus of claim 3 , wherein the p-type epitaxial region and the n-type tub of the parasitic PNP bipolar transistor are further electrically connected through a second resistor formed on the p-type substrate, the second resistor and the first resistor being connected electrically in series between the emitter and the base of the parasitic PNP bipolar transistor.

5. The apparatus of claim 1 , wherein the p-type epitaxial region, the n-type tub, the p-type tub, and the first n-type well region are configured to form a first parasitic PNPN silicon-controlled rectifier.

6. The apparatus of claim 3 , wherein the p-type tub comprises a p-type deep well layer disposed in the p-type substrate, a second p-type well region adjacent a first side of the first n-type well region, and a third p-type well region adjacent a first side of the second n-type well region, wherein the p-type deep well layer, the second p-type well region, and the third p-type well region are continuously electrically connected.

7. The apparatus of claim 6 , wherein the p-type tub is configured to be electrically floating.

8. The apparatus of claim 1 , wherein the second n-type region, the p-type tub, and the n-type tub are configured to form a second parasitic NPN bipolar transistor.

9. The apparatus of claim 1 , wherein the p-type epitaxial region and the n-type tub, the p-type tub, and the second n-type well region are configured to form a second parasitic PNPN silicon-controlled rectifier.

10. The apparatus of claim 3 , wherein the n-type tub comprises an n-type buried layer disposed in the p-type substrate, a third n-type well region adjacent a first side of the p-type tub, and a fourth n-type well region adjacent a second side of the p-type tub.

11. The apparatus of claim 10 , further comprising a fourth p-type well region adjacent a first side of the third n-type well region, and a fifth p-type well region adjacent a first side of the fourth n-type well region.

12. The apparatus of claim 11 , further comprising a second resistor formed on the p-type substrate adjacent the fourth n-type well region and the fifth p-type well region.

13. The apparatus of claim 1 , further comprising a first n-type active region disposed in the first n-type well region and a second n-type active region disposed in the second n-type well region.

14. The apparatus of claim 13 , further comprising a first pad and a second pad, wherein the first pad is electrically connected to the first n-type active region and the first p-type active region, and wherein the second pad is electrically connected to the second n-type active region and the second p-type active region.

15. The apparatus of claim 14 , further comprising a first electrical connection between a third p-type active region electrically connected to the p-type substrate at a substrate potential and a second electrical connection between one of first or second pads and the p-type substrate at the substrate potential.

16. The apparatus of claim 15 , wherein the first electrical connection has a first resistance and the second electrical connection has a second resistance, wherein the first resistance is higher than the second resistance.

17. The apparatus of claim 15 , wherein the third p-type active region is electrically connected to the emitter of the parasitic PNP bipolar transistor.

18. An apparatus comprising:
a p-type substrate;
a first n-type well region, a second n-type well region, and a first p-type well region configured to form an NPN bi-directional transistor formed in the p-type substrate;
a p-type tub surrounding the NPN bi-directional transistor and in physical contact with the first n-type well region, the second n-type well region and the first p-type well region;
an n-type tub surrounding the p-type tub;
a p-type epitaxial region surrounding the n-type tub;
wherein the first n-type well region, the p-type tub, and the n-type tub are configured to form a first parasitic NPN bipolar transistor;
wherein the p-type epitaxial region, the n-type tub, and the p-type tub are configured to form a parasitic PNP bipolar transistor;
wherein the p-type epitaxial region is configured to form an emitter of the parasitic PNP bipolar transistor, and wherein the n-type tub is configured to form a base of the parasitic PNP bipolar transistor;
wherein the emitter and the base of the parasitic PNP bipolar transistor are connected through a first resistor formed in the p-type epitaxial region;
wherein the n-type tub comprises an n-type buried layer disposed in the p-type substrate, a third n-type well region adjacent a first side of the p-type tub, and a fourth n-type well region adjacent a second side of the p-type tub; and
wherein the NPN bi-directional transistor is arranged in an annular configuration, wherein the first p-type well concentrically surrounds the first n-type well, and wherein the second n-type well concentrically surrounds the first p-type well.

19. The apparatus of claim 18 , wherein a third p-type well of the p-type tub surrounds the NPN bi-directional transistor, the fourth n-type well of the n-type tub surrounds the third p-type well, and the p-type epitaxial region surrounds the fourth n-type well.

20. The apparatus of claim 1 , wherein the p-type epitaxial region is electrically connected to the p-type substrate.

21. The apparatus of claim 11 , further comprising a fifth n-type well region adjacent a first side of the fifth p-type well region, and a sixth p-type well region adjacent a first side of the fifth n-type well region, wherein the p-type epitaxial region is disposed below each of the fifth p-type well region, the fifth n-type well region, and the sixth p-type well region.

22. The apparatus of claim 21 , wherein the first resistor has a first resistor resistance deriving at least in part from the p-type epitaxial region.

23. The apparatus of claim 22 , wherein the first resistor has a first resistance further deriving from the fifth p-type well region and the sixth p-type well region.

24. An apparatus comprising:
a p-type substrate;
a first n-type well

Assignees

• Analog Devices Inc

Inventors

• Salcedo Javier Alejandro
• Luo Juan

Classifications

• H10D89/713

  including a PNP transistor and a NPN transistor, wherein each of said transistors has its base region coupled to the collector region of the other transistor, e.g. silicon controlled rectifier [SCR] devices · CPC title

• H10D84/854 Primary

  comprising arrangements for preventing bipolar actions between the different IGFET regions, e.g. arrangements for latchup prevention · CPC title

• H10D84/619 Primary

  Combinations of lateral BJTs and one or more of diodes, resistors or capacitors · CPC title

• H01L27/0921

  Electricity · mapped topic

• H01L27/0262

  Electricity · mapped topic