Nitride semiconductor device including a horizontal switching device

Patent metadata

Field	Value
Publication number	US-10403745-B2
Application number	US-201615578403-A
Country	US
Kind code	B2
Filing date	Jun 14, 2016
Priority date	Jul 14, 2015
Publication date	Sep 3, 2019
Grant date	Sep 3, 2019

Abstract

A nitride semiconductor device includes a horizontal switching device that includes a substrate, a channel forming layer, a source region, a drain region and a gate region. The source region and the drain region are arranged apart from each other in one direction along a plane of the substrate. The gate region is formed of a p-type semiconductor layer and is arranged between the source region and the drain region. The gate region is divided into multiple parts in a perpendicular direction along the plane of the substrate, the perpendicular direction being perpendicular to an arrangement direction in which the source region and the drain region are arranged. Accordingly, on-resistance is decreased while securing high breakdown voltage.

First claim

The invention claimed is:

1. A nitride semiconductor device comprising
a horizontal switching device including:
a substrate that is formed of a semi-insulator or a semiconductor;
a channel forming layer that includes a first nitride semiconductor layer disposed above the substrate and a hetero-junction structure disposed above the first nitride semiconductor layer, the first nitride semiconductor layer providing an electron transit layer, the hetero-junction structure including at least one second nitride semiconductor layer and at least one third nitride semiconductor layer, the at least one second nitride semiconductor layer having a forbidden band width greater than the first nitride semiconductor layer and providing an electron donor portion, and the at least one third nitride semiconductor layer having a forbidden band width less than the at least one second nitride semiconductor layer;
a source region and a drain region that are arranged apart from each other in one direction along a plane of the substrate, the source region and the drain region extending from a surface of the channel forming layer and reaching the first nitride semiconductor layer; and
a gate region that is formed of a p-type semiconductor layer and is arranged between the source region and the drain region,

the horizontal switching device being configured to generate a current between the source region and the drain region by a 2-dimensional electron gas carrier and a 2-dimensional hole gas carrier, the 2-dimensional electron gas carrier being induced in the first nitride semiconductor layer adjacent to an interface between the first nitride semiconductor layer and the at least one second nitride semiconductor layer, and the 2-dimensional hole gas carrier being induced between the at least one second nitride semiconductor layer and the at least one third nitride semiconductor layer positioned above the at least one second nitride semiconductor layer, wherein
the gate region is divided into multiple parts stacked behind apart from each other in a perpendicular direction along the plane of the substrate, the perpendicular direction being perpendicular to a horizontal direction in which the source region and the drain region are arranged, the perpendicular direction further being perpendicular to a stack direction in which the first nitride semiconductor layer and the hetero-junction structure of the channel forming layer are stacked.

2. The nitride semiconductor device according to claim 1 , wherein
the gate region extends from a surface of the channel forming layer and reaches the first nitride semiconductor layer.

3. The nitride semiconductor device according to claim 1 , wherein
the gate region extends from the surface of the channel forming layer and reaches an intermediate position of the at least one second nitride semiconductor layer or the at least one third nitride semiconductor layer of the channel forming layer in a thickness direction.

4. The nitride semiconductor device according to claim 1 ,
wherein
a distance between adjacent two of the multiple parts of the gate region is less than a sum of a distance from the gate region to the source region and a length of the gate region in a direction from the gate region to the source region.

5. The nitride semiconductor device according to claim 1 , wherein
the at least one second nitride semiconductor layer includes a plurality of second nitride semiconductor layers,
the at least one third nitride semiconductor layer includes a plurality of third nitride semiconductor layers,
the plurality of second nitride semiconductor layers and the plurality of third nitride semiconductor layers provide multiple pairs each including one of the plurality of second nitride semiconductor layers and one of the plurality of third nitride semiconductor layers, and
the multiple pairs are stacked.

6. The nitride semiconductor device according to claim 5 , wherein
the gate region reaches an intermediate position in a thickness direction of one of the plurality of second nitride semiconductor layers positioned closest to the substrate or one of the plurality of third nitride semiconductor layers positioned closest to the substrate.

7. The nitride semiconductor device according to claim 1 ,
wherein
the first nitride semiconductor layer and the at least one third nitride semiconductor layer are formed of GaN,
the at least one second nitride semiconductor layer is formed of AlGaN, and
the p-type semiconductor layer is formed of p-type GaN.

8. The nitride semiconductor device according to claim 1 , further comprising
a MOS structure arranged between the gate region and the source region, the MOS structure including:
a recess that extends from the surface of the channel forming layer and reaches the first nitride semiconductor layer;
a gate insulation film that is disposed in the recess; and
a gate electrode that is disposed on the gate insulation film.

9. The nitride semiconductor device according to claim 8 , wherein the gate region has a potential fixed at a potential of the source region.

10. A nitride semiconductor device comprising a horizontal switching device including:
a substrate that is formed of a semi-insulator or a semiconductor;
a channel forming layer that includes a first nitride semiconductor layer disposed above the substrate and a hetero-junction structure disposed above the first nitride semiconductor layer, the first nitride semiconductor layer providing an electron transit layer, the hetero-junction structure including at least one second nitride semiconductor layer and at least one third nitride semiconductor layer, the at least one second nitride semiconductor layer having a forbidden band width greater than the first nitride semiconductor layer and providing an electron donor portion, and the at least one third nitride semiconductor layer having a forbidden band width less than the at least one second nitride semiconductor layer;
a source region and a drain region that are arranged apart from each other in one direction along a plane of the substrate, the source region and the drain region extending from a surface of the channel forming layer and reaching the first nitride semiconductor layer; and
a gate region that is formed of a p-type semiconductor layer and is arranged between the source region and the drain region,
the horizontal switching device being configured to generate a current between the source region and the drain region by a 2-dimensional electron gas carrier and a 2-dimensional hole gas carrier, the 2-dimensional electron gas carrier being induced in the first nitride semiconductor layer adjacent to an interface between the first nitride semiconductor layer and the at least one second nitride semiconductor layer, and the 2-dimensional hole gas carrier being induced between the at least one second nitride semiconductor layer and the at least one third nitride semiconductor layer positioned above the at least one second nitride semiconductor layer,
wherein
the source region and the drain region are arranged in a first row in a horizontal direction,
the gate region is divided into multiple parts stacked behind apart from each other that are arranged in a second row in a perpendicular direction along the plane of the substrate, and
the perpendicular direction is perpendicular to the horizontal direction.

Assignees

• Denso Corp

Inventors

• Higuchi Yasushi
• Hoshi Shinichi
• Oyama Kazuhiro

Classifications

• H01L29/2003

  Electricity · mapped topic

• H01L29/407

  Electricity · mapped topic

• H01L29/4236

  Electricity · mapped topic

• H01L29/0843

  Electricity · mapped topic

• H01L29/78

  Electricity · mapped topic