Semiconductor devices with regrown contacts and methods of fabrication

Patent metadata

Field	Value
Publication number	US-10403718-B2
Application number	US-201715856442-A
Country	US
Kind code	B2
Filing date	Dec 28, 2017
Priority date	Dec 28, 2017
Publication date	Sep 3, 2019
Grant date	Sep 3, 2019

Abstract

An embodiment of a semiconductor device includes a semiconductor substrate that includes a channel, a first dielectric layer disposed over the semiconductor substrate, and a regrown contact formed through a first opening in the first dielectric layer. The regrown contact includes a regrown region formed over the semiconductor substrate, an overhang region coupled to the regrown region and formed over the first dielectric layer, adjacent the first opening, and a conductive cap formed over the regrown region and the overhang region. A method for fabricating the semiconductor device includes forming the first dielectric layer over the semiconductor substrate, forming the first opening in the first dielectric layer, forming a regrown semiconductor layer within the first opening and over the first dielectric layer, forming a conductive cap over the regrown semiconductor layer, and etching the regrown semiconductor layer outside the conductive cap.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor substrate that includes an upper surface and a channel;
a first dielectric layer disposed over the upper surface of the semiconductor substrate; and
a regrown contact formed over and within the semiconductor substrate comprising:
a first opening formed in the first dielectric layer;
a regrown region formed within the first opening and electrically coupled to the channel;
an overhang region comprising a semiconductor material coupled to the regrown region and formed over the first dielectric layer, adjacent the first opening; and
a conductive cap formed over the regrown region and the overhang region.

2. The semiconductor device of claim 1 , further comprising a second dielectric layer disposed between the semiconductor substrate and the first dielectric layer, wherein the regrown region extends through a second opening in the second dielectric layer.

3. The semiconductor device of claim 1 , further comprising a third dielectric layer disposed between the semiconductor substrate and the second dielectric layer, wherein the regrown region extends through a third opening in the third dielectric layer.

4. The semiconductor device of claim 1 , wherein the regrown contact is configured as one or more source/drain regions.

5. The semiconductor device of claim 1 wherein the conductive cap is gold-free.

6. The semiconductor device of claim 1 , wherein the regrown contact is configured as a gate electrode formed above the channel and electrically coupled to the channel.

7. The semiconductor device of claim 1 , wherein the semiconductor substrate comprises a group-III nitride semiconductor.

8. The semiconductor device of claim 2 , wherein the second dielectric layer is configured as an etch stop layer resistant to an etchant of the first dielectric layer.

9. The semiconductor device of claim 4 , further comprising a gate electrode formed over the semiconductor substrate adjacent to and between the source/drain regions.

10. The semiconductor device of claim 9 , wherein the gate electrode extends through a first gate opening and forms a Schottky contact with the semiconductor substrate.

11. The semiconductor device of claim 9 , further comprising a gate dielectric layer disposed within the first gate opening, between the semiconductor substrate and a bottom portion of the gate electrode.

12. The semiconductor device of claim 6 , wherein the regrown region of the regrown contact comprises a p-type dopant and forms a p-n junction with the semiconductor substrate.

13. The semiconductor device of claim 6 , further comprising source/drain regions formed over the semiconductor substrate through source/drain openings in the first dielectric layer, electrically coupled to the channel, and laterally adjacent the gate electrode, the gate electrode being disposed between the source/drain regions.

14. The semiconductor device of claim 13 , wherein the source/drain regions comprise regrown contacts.

15. A group-III nitride transistor comprising:
a semiconductor substrate that includes a group-III nitride layer, an upper surface, and a channel;
a first dielectric layer disposed over the upper surface of the semiconductor substrate;
a gate electrode formed over the semiconductor substrate and through the first dielectric layer; and
a regrown contact formed over and within the semiconductor substrate comprising:
a first opening formed in the first dielectric layer;
a regrown region formed within the first opening and electrically coupled to the channel;
an overhang region comprising a semiconductor material coupled to the regrown region and formed over the first dielectric layer, adjacent the first opening;
a conductive cap formed over the regrown region and the overhang region; and
a second dielectric layer, configured as an etch stop layer resistant to an etchant of the first dielectric layer, disposed between the semiconductor substrate and the first dielectric layer, wherein the regrown region extends through a second opening in the second dielectric layer.

16. The semiconductor device of claim 15 , wherein the gate extends through the first dielectric layer within a first gate opening and the second dielectric layer through a second gate opening, forming a Schottky contact with the semiconductor layer.

17. The semiconductor device of claim 15 , wherein a gate dielectric is disposed between the gate electrode and the semiconductor substrate, forming a metal-insulator-semiconductor junction.

18. The semiconductor device of claim 15 , further comprising a third dielectric layer formed between the second dielectric layer and the semiconductor substrate.

19. The semiconductor device of claim 16 , wherein the gate extends through the first dielectric layer and second dielectric layer, forming a Schottky junction.

20. A method for fabricating a semiconductor device, the method comprising:
providing a semiconductor substrate that includes an upper surface and a channel;
forming a first dielectric layer over the upper surface of the semiconductor substrate;
forming a first opening in the first dielectric layer;
forming a regrown semiconductor layer over the first dielectric layer and over the semiconductor substrate through the first opening;
forming a conductive cap over the first opening; and
etching an exterior portion of the regrown semiconductor layer, forming a regrown region within the first opening, wherein the regrown region is coupled to an overhang region, over the first dielectric layer, outside the first opening, and under the cap.

21. The method of claim 20 , further comprising forming a second dielectric layer, configured as an etch stop resistant to an etchant of the first dielectric layer, over the upper surface of the semiconductor substrate and forming a second opening in the second dielectric layer through which the regrown semiconductor layer passes.

22. The method of claim 20 , wherein forming the conductive cap includes dry etching.

23. The method of claim 20 , further comprising forming a gate electrode.

24. The method of claim 20 , further comprising creating isolation regions within and along the upper surface of the semiconductor substrate to define an active area.

Assignees

• Nxp Usa Inc

Inventors

• Huang Jenn Hwa
• Yue Yuanzheng

Classifications

• H01L29/0891 Primary

  Electricity · mapped topic

• H01L29/66636

  Electricity · mapped topic

• H01L29/0847

  Electricity · mapped topic

• H01L29/778

  Electricity · mapped topic

• H01L29/78

  Electricity · mapped topic