Semiconductor packages and methods of packaging semiconductor devices

Patent metadata

Field	Value
Publication number	US-10403592-B2
Application number	US-201715726409-A
Country	US
Kind code	B2
Filing date	Oct 6, 2017
Priority date	Mar 14, 2013
Publication date	Sep 3, 2019
Grant date	Sep 3, 2019

Abstract

Semiconductor packages and methods for forming a semiconductor package are disclosed. The method includes providing a package substrate having first and second major surfaces. The package substrate includes a base substrate having a mold material and a plurality of interconnect structures including via contacts extending through the first to the second major surface of the package substrate. A die having conductive contacts on its first or second surface is provided. The conductive contacts of the die are electrically coupled to the interconnect structures. A cap is formed over the package substrate to encapsulate the die.

First claim

What is claimed is:

1. A method for forming a semiconductor package comprising:
providing a package substrate having planar first and second major surfaces, wherein the package substrate comprises a base substrate having a mold material and a plurality of via contacts extending from the first to the second major surface of the package substrate;
forming an adhesive directly on a first major surface of the base substrate, wherein the via contacts extend above the first major surface of the base substrate and the adhesive is about aligned to sides of the via contacts;
forming an insulating layer directly over the adhesive and the via contacts, wherein the insulating layer comprises a first and a second major surface;
forming a plurality of conductive studs over the adhesive, wherein the conductive studs are positioned in the insulating layer and extend from the first to the second major surface of the insulating layer, wherein a width of the conductive studs is smaller than a width of the via contacts;
forming conductive traces and connection pads directly on the first major surface of the insulating layer, wherein the conductive traces and connection pads are positioned over the conductive studs;
providing a die having conductive contacts, wherein the conductive contacts of the die are electrically coupled to the conductive traces or connection pads; and
forming a cap over the package substrate to encapsulate the die, wherein a bottom of the cap contacts the conductive traces and the first major surface of the insulating layer.

2. The method of claim 1 wherein the insulating layer electrically isolates the plurality of conductive studs from each other, wherein a top surface of the conductive studs is coplanar to the first major surface of the insulating layer.

3. The method of claim 1 wherein forming the adhesive comprises performing a lamination technique to form a UV sensitive laminate layer on the base substrate, and performing mask and etch techniques to pattern the UV sensitive laminate layer and form the adhesive.

4. The method of claim 1 wherein the conductive studs are formed after forming the adhesive and prior to forming the insulating layer.

5. The method of claim 4 wherein the insulating layer is formed around the conductive studs and a top surface of the conductive studs is substantially coplanar with the top surface of the insulating layer.

6. The method of claim 4 wherein forming the plurality of conductive studs comprises performing a mask and etch process to pattern a first and a second conductive layer to form the conductive studs.

7. The method of claim 6 wherein the first conductive layer comprises a different conductive material to the second conductive layer to define multi-layered conductive studs.

8. The method of claim 1 wherein forming the conductive studs comprises performing a mask and etch process to pattern a first conductive layer to form the conductive studs.

9. The method of claim 1 wherein forming the plurality of conductive studs comprises performing a mask and etch process to pattern a first and a second conductive layer to form the conductive studs; and
further comprises coupling die pads on the die to the conductive traces with wire bonds.

10. The method of claim 1 wherein forming the insulating layer comprises performing a molding or a lamination technique.

11. The method of claim 1 where forming the conductive traces and the connection pads comprises performing a plating process.

12. A method for forming a semiconductor package comprising:
providing a package substrate having first and second major surfaces, wherein the package substrate comprises a base substrate a plurality of via contacts extending from the first to the second major surface of the package substrate;
forming an adhesive on a first major surface of the base substrate, wherein the via contacts extend above the first major surface of the base substrate and the adhesive is about aligned to sides of the via contacts;
forming an insulating layer over the adhesive and the via contacts, wherein the insulating layer comprises first and second insulating major surface;
forming a plurality of conductive studs over the adhesive, wherein the conductive studs are positioned in the insulating layer and extend from the first to the second major surface of the insulating layer, wherein a width of the conductive studs is smaller than a width of the via contacts;
forming conductive traces and connection pads on the first insulating major surface, wherein the conductive traces and connection pads are positioned over the conductive studs;
providing a die having conductive contacts, wherein the conductive contacts of the die are electrically coupled to the conductive traces or connection pads; and
forming a cap over the package substrate to encapsulate the die, wherein a bottom of the cap contacts the conductive traces and the first major surface of the insulating layer.

13. The method of claim 12 wherein the insulating layer electrically isolates the plurality of conductive studs from each other, wherein a top surface of the conductive studs is coplanar to the first major surface of the insulating layer.

14. The method of claim 12 wherein forming the adhesive comprises performing a lamination technique to form a UV sensitive laminate layer on the base substrate, and performing mask and etch techniques to pattern the UV sensitive laminate layer and form the adhesive.

15. The method of claim 12 wherein the conductive studs are formed after forming the adhesive and prior to forming the insulating layer.

16. The method of claim 15 wherein the insulating layer is formed around the conductive studs and a top surface of the conductive studs is substantially coplanar with the top surface of the insulating layer.

17. The method of claim 15 wherein forming the plurality of conductive studs comprises performing a mask and etch process to pattern a first and a second conductive layer to form the conductive studs.

18. The method of claim 17 wherein the first conductive layer comprises a different conductive material to the second conductive layer to define multi-layered conductive studs.

19. The method of claim 12 wherein forming the conductive studs comprises performing a mask and etch process to pattern a first conductive layer to form the conductive studs.

20. The method of claim 12 wherein forming the plurality of conductive studs comprises performing a mask and etch process to pattern a first and a second conductive layer to form the conductive studs; and
further comprises coupling die pads on the die to the conductive traces with wire bonds.

Assignees

• Utac Headquarters Pte Ltd
• United Test And Assembly Center Ltd

Inventors

• Yang Yongbo
• Dimaano Antonio Jr Bambalan
• Wo Chun Hong

Classifications

• H10P72/74

  using temporarily an auxiliary support · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title