Method to form hybrid SiGe fin

Patent metadata

Field	Value
Publication number	US-10403546-B2
Application number	US-201815925326-A
Country	US
Kind code	B2
Filing date	Mar 19, 2018
Priority date	Mar 21, 2017
Publication date	Sep 3, 2019
Grant date	Sep 3, 2019

Abstract

A method for manufacturing a semiconductor device includes providing a semiconductor structure having a semiconductor substrate, a dielectric layer on the semiconductor substrate, and a hardmask on a second portion of the dielectric layer while exposing a first portion of the dielectric layer; forming a copolymer on the semiconductor structure; performing an annealing treatment such that the copolymer forms a staggered configuration of a first monomer and a second monomer; removing the first monomer; performing a first etching process on the first portion using the second monomer as a mask to form a first trench extending to the semiconductor substrate; removing the second monomer and the first hardmask; and epitaxially growing a first semiconductor fin in the first trench.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device, comprising:
providing a semiconductor structure including a semiconductor substrate, a dielectric layer on the semiconductor substrate, and a hardmask on a second portion of the dielectric layer while exposing a first portion of the dielectric layer;
forming a copolymer on the semiconductor structure;
performing an annealing treatment such that the copolymer forms a staggered configuration of a first monomer and a second monomer;
removing the first monomer;
performing a first etching process on the first portion using the second monomer as a mask to form a first trench extending to the semiconductor substrate;
removing the second monomer and the first hardmask; and
epitaxially growing a first semiconductor fin in the first trench.

2. The method of claim 1 , further comprising:
forming a second trench in the second portion extending to the semiconductor substrate;
epitaxially growing a second semiconductor fin in the second trench.

3. The method of claim 2 , wherein the first semiconductor fin and the second semiconductor fin each comprise a SiGe fin.

4. The method of claim 3 , wherein the first semiconductor fin and the second semiconductor fin each comprise a Ge content that gradually changes from bottom to top.

5. The method of claim 4 , wherein the Ge content of the first semiconductor fin gradually increases from bottom to top, and the Ge content of the second semiconductor fin gradually decreases from bottom to top.

6. The method of claim 4 , wherein the Ge content of the first semiconductor fin gradually decreases from bottom to top, and the Ge content of the second semiconductor fin gradually increases from bottom to top.

7. The method of claim 2 , wherein forming the second trench in the second portion comprises:
forming a second hardmask on the first portion of the dielectric layer;
forming a second copolymer on the second hardmask and the second portion;
performing a second annealing treatment such that the second copolymer forms a staggered configuration of a third monomer and a fourth monomer;
removing the third monomer;
performing a second etching process on the second portion using the fourth monomer as a mask to form the second trench extending to the semiconductor substrate;
removing the forth monomer and the second hardmask.

8. The method of claim 7 , wherein:
the first copolymer and the second copolymer comprise a same material;
the first monomer and the third monomer comprise a same material;
the second monomer and the fourth monomer comprise a same material.

9. The method of claim 2 , further comprising:
etching back the dielectric layer such that an upper surface of the etched back dielectric layer is lower than an upper surface of the first semiconductor fin and the second semiconductor fin.

10. The method of claim 1 , wherein the first copolymer comprises polystyrene-block-polymethylmethacrylate (PS-b-PMMA).

11. The method of claim 10 , wherein the first monomer comprises polymethylmethacrylate and the second monomer comprises polystyrene.

12. The method of claim 11 , wherein the first monomer has a cross-sectional width greater a cross-sectional width of the second monomer.

13. The method of claim 1 , wherein forming the copolymer comprises a spin coating process.

14. The method of claim 1 , wherein removing the first monomer comprises:
performing an ultraviolet (UV) curing treatment on the first monomer;
removing the first monomer by washing with CH 3 COOH.

15. The method of claim 1 , wherein removing the second monomer comprises a reactive ion etching process.

16. The method of claim 1 , wherein the annealing treatment is performed at a temperature in a range between 80° C. and 150° C.

Assignees

• Semiconductor Mfg Int Shanghai Corp
• Semiconductor Mfg Int Beijing Corp

Inventors

• Deng Hao
• Xu Jianhua
• Zhou Feng
• Yang Xiaojun

Classifications

• H01L21/823412

  Electricity · mapped topic

• H01L21/823431 Primary

  Electricity · mapped topic

• H01L27/0886

  Electricity · mapped topic

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title