Backside redistribution layer patch antenna

Patent metadata

Field	Value
Publication number	US-10403511-B2
Application number	US-201313740428-A
Country	US
Kind code	B2
Filing date	Jan 14, 2013
Priority date	Jan 14, 2013
Publication date	Sep 3, 2019
Grant date	Sep 3, 2019

Abstract

A patch antenna system comprising: an integrated circuit die having an active side including an active layer, and a backside; a dielectric layer formed on the backside; and a redistribution layer formed on the dielectric layer wherein the redistribution layer forms an array of patches. The patch antenna further comprises a plurality of through-silicon vias (TSV), wherein the TSVs electrically connect the array of patches to the active layer.

First claim

What is claimed is:

1. An on-chip antenna comprising:
an integrated circuit formed in a semiconductor material, the integrated circuit comprising:
an active layer, a backside composed of the semiconductor material, and a ground plane;
wherein the backside composed of the semiconductor material forms the ground plane;
a dielectric layer provided over the ground plane;
a redistribution layer provided over the dielectric layer, the redistribution layer comprising one or more patch antenna elements, wherein a length of the one or more patch antenna elements is proportional to a thickness of the dielectric layer and/or a dielectric constant of the dielectric layer; and
wherein the ground plane is located between the active layer and the dielectric layer.

2. The on-chip antenna of claim 1 ,
wherein the dielectric layer is formed by a silicon dioxide layer.

3. The on-chip antenna of claim 1 ,
wherein the one or more patch antenna elements comprise a phased array.

4. A patch antenna system comprising:
an integrated circuit formed in a semiconductor material, the integrated circuit comprising:
an active layer, a backside composed of the semiconductor material forming a ground plane;
a dielectric layer provided over the ground plane;
a redistribution layer provided over the dielectric layer, the redistribution layer comprising one or more patch antenna elements, wherein a length of the one or more patch antenna elements is proportional to a thickness of the dielectric layer and/or a dielectric constant of the dielectric layer;
wherein the ground plane is located between the active layer and the dielectric layer; and
wherein the active layer comprises at least one transceiver and at least one baseband signal processor circuit.

5. The patch antenna system of claim 4 ,
wherein the integrated circuit is mounted on a flip chip package in a flip chip configuration.

6. The patch antenna system of claim 4 further comprising:
through silicon via structures connecting the patch antenna elements and the at least one transceiver and the at least one baseband signal processor circuit.

7. The patch antenna system of claim 6 further comprising:
a plurality of the one or more patch antenna elements electrically connected by at least one through silicon via structure to: a plurality of the at least one transceivers and a plurality of the at least one baseband signal processing circuits; and
wherein the patch antenna elements comprise a phased array.

8. The patch antenna system of claim 4 ,
wherein the operating frequency of the system is from 57 GHz to 64 GHz and the width of the one more patch antenna elements is from 0.98 mm to 1.58 mm.

9. An integrated circuit formed in a semiconductor material comprising:
a substrate comprising an active layer and a backside composed of the semiconductor material forming a ground plane;
a dielectric layer provided over the ground plane;
a redistribution layer provided over the dielectric layer, the redistribution layer formed over the backside composed of the semiconductor material and comprising one or more patch antenna elements, wherein a length of the one or more patch antenna elements is proportional to a thickness of the dielectric layer and/or a dielectric constant of the dielectric layer; and
wherein the ground plane is a reflector located between the active layer and the dielectric layer.

10. A method of fabricating a patch antenna comprising:
providing an integrated circuit die composed of a semiconductor material, the integrated circuit die comprising:
an active layer and a backside composed of the semiconductor material, the backside composed of the semiconductor material forming a ground plane;

forming a dielectric layer directly on the backside composed of the semiconductor material, wherein the ground plane is located between the active layer and the dielectric layer; and
forming a redistribution layer on the dielectric layer, the redistribution layer comprising one or more patch antenna elements, wherein a length of the one or more patch antenna elements is proportional to a thickness of the dielectric layer and/or a dielectric constant of the dielectric layer.

11. The method of claim 10 further comprising:
forming one or more through silicon vias electrically connecting the one or more patch antenna elements to the active layer.

Assignees

• Intel Corp

Inventors

• Saraswat Ruchir
• Cowley Nicholas P
• Zillmann Uwe

Classifications

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title

• H10W20/497

  Inductive arrangements or effects of, or between, wiring layers · CPC title

• H10W20/423

  Shielding layers · CPC title

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/20 Primary

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title