Preventing data corruption and single point of failure in a fault-tolerant memory

Patent metadata

Field	Value
Publication number	US-10402287-B2
Application number	US-201515500064-A
Country	US
Kind code	B2
Filing date	Jan 30, 2015
Priority date	Jan 30, 2015
Publication date	Sep 3, 2019
Grant date	Sep 3, 2019

Abstract

According to an example, data corruption and single point of failure is prevented in a fault-tolerant memory fabric with multiple redundancy controllers by granting, by a parity media controller, a lock of a stripe to a redundancy controller to perform a sequence on the stripe. The lock may be broken in response to determining a failure of the redundancy controller prior to completing the sequence. In response to breaking the lock, the parity cacheline of the stripe may be flagged as invalid. Also, a journal may be updated to document the breaking of the lock.

First claim

What is claimed is:

1. A method for preventing data corruption and single point of failure in a fault-tolerant memory fabric with multiple redundancy controllers, the method comprising:
granting, by a media controller, a first lock of a stripe to a first redundancy controller to perform a sequence on the stripe;
breaking the first lock in response to determining a failure of the first redundancy controller prior to completing the sequence;
flagging a parity cacheline of the stripe as invalid in response to breaking the first lock; and
updating a journal to document the breaking of the first lock.

2. The method of claim 1 , wherein determining the failure of the first redundancy controller comprises determining that a duration of the first lock has exceeded a predetermined time threshold.

3. The method of claim 1 , wherein flagging the parity cacheline of the stripe further comprises granting a second lock for the stripe to a second redundancy controller.

4. The method of claim 3 , wherein granting the second lock for the stripe to the second redundancy controller comprises transmitting an indication that the parity cacheline of the stripe has been flagged as invalid with the grant of the second lock.

5. The method of claim 4 , wherein transmitting the indication further comprises triggering the second redundancy controller to initiate a rebuild sequence of the stripe.

6. The method of claim 1 , wherein updating the journal to document the breaking of the first lock further comprises:
transmitting an entry of the journal to a firmware health monitor, wherein the transmitted entry triggers a rebuild sequence of the stripe by a second redundancy controller.

7. A media controller to prevent data corruption and single point of failure in a fault-tolerant memory fabric with multiple redundancy controllers, the media controller comprising:
a lock grant module to grant a first lock for a stripe to a first redundancy controller;
a duration determination module to determine that a duration of the first lock has exceeded a predetermined time threshold,
a lock break module to break the first lock of the stripe;
a flag module to flag a parity cacheline of the stripe as invalid; and
a journal update module to update a journal to document the breaking of the first lock.

8. The media controller of claim 7 , wherein to flag the parity cacheline of the stripe, the flag module is to grant a second lock for the stripe to a second redundancy controller.

9. The media controller of claim 8 , wherein to grant the second lock for the stripe to the second redundancy controller, the lock grant module is to transmit an indication that the parity cacheline of the stripe has been flagged as invalid with the grant of the second lock.

10. The media controller of claim 9 , wherein to transmit the indication, the lock grant module is to initiate a rebuild sequence of the stripe.

11. The media controller of claim 7 , wherein to update the journal to document the breaking of the first lock, the journal update module is to:
transmit an entry of the journal to a firmware health monitor, wherein the transmitted entry triggers a rebuild sequence of the stripe by a second redundancy controller.

12. A non-transitory computer readable medium to prevent data corruption and single point of failure in a fault-tolerant memory, including machine readable instructions executable by a processor to:
break a first lock of a stripe in response to determining that a duration of the first lock has exceeded a predetermined time threshold;
flag a parity cacheline of the stripe as invalid; and
update a journal to document the breaking of the first lock.

13. The non-transitory computer readable medium of claim 12 , wherein to flag the parity cacheline of the stripe, the machine readable instructions are executable by the processor to:
grant a second lock for the stripe to an operating redundancy controller; and
transmit an indication that the parity cacheline of the stripe has been flagged as invalid with the grant of the second lock.

14. The non-transitory computer readable medium of claim 13 , wherein to transmit the indication, the machine readable instructions are executable by the processor to trigger the operating redundancy controller to initiate a rebuild sequence of the stripe.

15. The non-transitory computer readable medium of claim 12 , wherein to update the journal to document the breaking of the first lock, the machine readable instructions are executable by the processor to:
update an entry of the journal to a firmware health monitor, wherein the entry triggers a rebuild sequence of the stripe by a second redundancy controller.

Assignees

• Hewlett Packard Entpr Dev Lp

Inventors

• Sherlock Derek Alan
• Ray Harvey
• Brueggen Chris Michael

Classifications

• G06F11/108 Primary

  Parity data distribution in semiconductor storages, e.g. in SSD · CPC title

• G06F11/2092 Primary

  Techniques of failing over between control units · CPC title

• G06F11/2094

  Redundant storage or storage space (G06F11/2056 takes precedence) · CPC title

• G06F2201/805

  Real-time · CPC title