Methods and apparatus to compile code to generate data flow code

Patent metadata

Field	Value
Publication number	US-10402176-B2
Application number	US-201715855964-A
Country	US
Kind code	B2
Filing date	Dec 27, 2017
Priority date	Dec 27, 2017
Publication date	Sep 3, 2019
Grant date	Sep 3, 2019

Abstract

Methods, apparatus, systems and articles of manufacture to compiler compile code to generate dataflow code are described. An example compiler apparatus includes an intermediate representation transformer to transform input software code to intermediate representation code; an instruction selector to insert machine instructions of a target execution platform in the intermediate representation code to generate machine intermediate representation code; and a target machine transformer to: convert a portion of the machine intermediate representation code to dataflow code to generate dataflow intermediate representation code; and allocate registers within the dataflow intermediate representation code.

First claim

What is claimed is:

1. A compiler apparatus comprising:
a memory;
a processor circuitry;
an intermediate representation transformer to transform input software code to intermediate representation code;
an instruction selector to insert machine instructions of a target execution platform in the intermediate representation code to generate machine intermediate representation code; and
a dataflow converter to convert a portion of the machine intermediate representation code to dataflow code to generate dataflow intermediate representation code including:
selecting a first region of the machine intermediate representation code;
converting the first region to the dataflow code prior to converting a second region, wherein the first region is contained within the second region;
performing a live range analysis to identify a live range when variables in the machine intermediate representation code are active, and
assigning a latency insensitive channel to the live range; and,

a target machine transformer to allocate registers within the dataflow intermediate representation code, wherein at least one of the intermediate representation transformer, the instruction selector, the dataflow converter, or the target machine transformer is implemented by the processor circuitry.

2. The compiler apparatus as defined in claim 1 , wherein the dataflow converter is to generate machine specific instructions of the target execution platform for at least one of a join or a split included in the machine intermediate representation code.

3. The compiler apparatus as defined in claim 1 , wherein the dataflow converter is to move operations converted to dataflow code onto dataflow units of the target execution platform.

4. The compiler apparatus as defined in claim 1 , wherein the dataflow converter is to remove branches from the machine intermediate representation code.

5. The compiler apparatus as defined in claim 1 , wherein the target execution platform is a spatial accelerator.

6. A non-transitory computer readable medium comprising instructions that, when executed, cause a machine to at least:
transform input software code to intermediate representation code;
insert machine instructions of a target execution platform in the intermediate representation code to generate machine intermediate representation code;
convert a portion of the machine intermediate representation code to dataflow code to generate dataflow intermediate representation code including:
selecting a first region of the machine intermediate representation code;
converting the first region to the dataflow code prior to converting a second region, wherein the first region is contained within the second region;
performing a live range analysis to identify a live range when variables in the machine intermediate representation code are active, and assigning a latency insensitive channel to the live range; and

allocate registers within the dataflow intermediate representation code.

7. The non-transitory computer readable medium as defined in claim 6 , wherein the instructions, when executed, cause the machine to generate machine specific instructions of the target execution platform for at least one of a join or a split included in the machine intermediate representation code.

8. The non-transitory computer readable medium as defined in claim 6 , wherein the instructions, when executed, cause the machine to move operations converted to dataflow code onto dataflow units of the target execution platform.

9. The non-transitory computer readable medium as defined in claim 6 , wherein the instructions, when executed, cause the machine to remove branches from the machine intermediate representation code.

10. The non-transitory computer readable medium as defined in claim 6 , wherein the target execution platform is a spatial accelerator.

11. A method comprising:
transforming, by executing an instruction with a processor, input software code to intermediate representation code;
inserting, by executing an instruction with a processor, machine instructions of a target execution platform in the intermediate representation code to generate machine intermediate representation code;
converting, by executing an instruction with a processor, a portion of the machine intermediate representation code to dataflow code to generate dataflow intermediate representation code including:
selecting a first region of the machine intermediate representation code;
converting the first region to the dataflow code prior to converting a second region, wherein the first region is contained within the second region;

performing a live range analysis to identify a live range when variables in the machine intermediate representation code are active, and
assigning a latency insensitive channel to the live range; and

allocating, by executing an instruction with a processor, registers within the dataflow intermediate representation code.

12. The method as defined in claim 11 , further including generating machine specific instructions of the target execution platform for at least one of a join or a split included in the machine intermediate representation code.

13. The method as defined in claim 11 , further including moving operations converted to dataflow code onto dataflow units of the target execution platform.

14. The method as defined in claim 11 , further including removing branches from the machine intermediate representation code.

15. The method as defined in claim 11 , wherein the target execution platform is a spatial accelerator.

Assignees

• Intel Corp

Inventors

• Glossop Kent
• Fleming Kermin
• Zhang Yongzhi
• Steely Jr Simon
• Sukha Jim
• Srinivasan Uma

Classifications

• G06F8/4441

  Reducing the execution time required by the program code · CPC title

• G06F8/433 Primary

  Dependency analysis; Data or control flow analysis · CPC title

• G06F8/441

  Register allocation; Assignment of physical memory space to logical memory space · CPC title

• G06F8/443

  Optimisation · CPC title

• G06F8/447

  Target code generation · CPC title