Interconnect structures for assembly of semiconductor structures including superconducting integrated circuits

Patent metadata

Field	Value
Publication number	US-10396269-B2
Application number	US-201615342478-A
Country	US
Kind code	B2
Filing date	Nov 3, 2016
Priority date	Nov 5, 2015
Publication date	Aug 27, 2019
Grant date	Aug 27, 2019

Abstract

A multi-layer semiconductor structure includes a first semiconductor structure and a second semiconductor structure, with at least one of the first and second semiconductor structures provided as a superconducting semiconductor structure. The multi-layer semiconductor structure also includes one or more interconnect structures. Each of the interconnect structures is disposed between the first and second semiconductor structures and coupled to respective ones of interconnect pads provided on the first and second semiconductor structures. Additionally, each of the interconnect structures includes a plurality of interconnect sections. At least one of the interconnect sections includes at least one superconducting and/or a partially superconducting material.

First claim

What is claimed is:

1. A multi-layer semiconductor structure, comprising:
a first semiconductor structure having first and second opposing surfaces and including one or more interconnect pads disposed on at least one of the first and second surfaces;
a second semiconductor structure having first and second opposing surfaces and including one or more interconnect pads disposed on at least one of the first and second surfaces, wherein at least one of the first and second semiconductor structures is a superconducting semiconductor structure; and
one or more interconnect structures, each of the interconnect structures disposed between the first and second semiconductor structures and coupled to respective ones of the interconnect pads provided on the first and second semiconductor structures, and each of the interconnect structures including a plurality of interconnect sections, wherein at least one of the interconnect sections includes at least one superconducting and/or a partially superconducting material;
wherein each of the interconnect structures has first and second opposing portions and includes:
a first interconnect section having first and second opposing portions, wherein the first portion of the first interconnect section corresponds to the first portion of the interconnect structure;
a second interconnect section having first and second opposing portions, wherein the first portion of the second interconnect section is disposed over the second portion of the first interconnect section; and
a third interconnect section having first and second opposing portions, wherein the first portion of the third interconnect section is disposed over the second portion of the second interconnect section, and the second portion of the third interconnect section corresponds to the second portion of the interconnect structure;
wherein the first interconnect section includes a plurality of conductive layers, and each of the conductive layers includes a different, respective metal or alloy material or combination of materials; and
wherein the third interconnect section includes a plurality of conductive layers, and each of the conductive layers includes a different, respective metal or alloy material or combination of materials;
wherein each of the conductive layers has a different, respective melting point;
wherein:
the first interconnect section of the first semiconductor structure consists of a first superconducting layer, a second superconducting layer disposed on the first superconducting layer, and a third conductive layer disposed on the second superconducting layer,
the second interconnect section of the first semiconductor structure consists of a superconducting bump disposed on the third layer of the first interconnect section; and
the third interconnect section of the first semiconductor structure consists of a fourth superconducting layer, a fifth superconducting layer disposed on the fourth superconducting layer, and a sixth conductive layer disposed on the fifth superconducting layer;
wherein at least one of the first, second, and third interconnect sections comprise an interface with a second one of the first, second, and third interconnect sections corresponding to a multi-melt interface that includes at least one superconducting and/or a partially superconducting material.

2. The multi-layer semiconductor structure of claim 1 wherein each of the interconnect sections includes one or more electrically conductive materials, and each of interconnect sections has a different, respective melting point than other ones of the interconnect sections.

3. The multi-layer semiconductor structure of claim 1 wherein a first one of the conductive layers includes Titanium (Ti) and/or Lead (Pb), a second one of the conductive layers includes Platinum (Pt) and/or Tin (Sn), and a third one of the conductive layers includes Gold (Au) and/or Indium (In).

4. The multi-layer semiconductor structure of claim 1 wherein the third interconnect section includes a plurality of conductive layers, and each of the conductive layers includes a different, respective metal or alloy material or combination of materials.

5. The multi-layer semiconductor structure of claim 1 wherein the first interconnect section and the third interconnect section are both provided as under bump metals (UBMs).

6. The multi-layer semiconductor structure of claim 5 wherein the second interconnect section is provided as a micro-bump.

7. The multi-layer semiconductor structure of claim 1 , wherein the first semiconductor has a first package pitch and the second semiconductor structure has a second package pitch, and one or more characteristics of the interconnect structures are selected based upon at least one of the first package pitch and the second package pitch.

8. The multi-layer semiconductor structure of claim 7 wherein the one or more characteristics include dimensions of the interconnect structures and materials of the interconnect structures.

9. The multi-layer semiconductor structure of claim 1 wherein the interconnect structures form a micro bump assembly on at least one of the first and second semiconductor structures.

10. The multi-layer semiconductor structure of claim 1 wherein the first semiconductor structure is a multi-chip module (MCM) or an interposer module.

11. The multi-layer semiconductor structure of claim 1 wherein the second semiconductor structure includes a qubit.

12. The multi-layer semiconductor structure of claim 1 , wherein:
the one or more interconnect pads includes Aluminum (Al) and/or Niobium (Nb), the first and fourth one of the conductive layers includes Titanium (Ti) and/or Lead (Pb) and/or Titanium nitride (TiN), the second and fifth one of the conductive layers includes Platinum (Pt) and/or Tin (Sn) and/or or Titanium nitride (TiN), and the third and sixth one of the conductive layers includes Gold (Au) and/or Indium (In);
the first, second, third, fourth, fifth, and sixth conductive layers each includes the different, respective metal or alloy material or combination of materials;
the first-second-third layers and the fourth-fifth-sixth layers are provided as under bump metals (UBMs); and
the second interconnect section is provided as a solder ball, sphere, pillar, or micro-bump.

Assignees

• Massachusetts Inst Technology

Inventors

• Oliver William D
• Kerman Andrew J
• Das Rabindra N
• Yost Donna-Ruth W
• Rosenberg Danna
• Gouker Mark A

Classifications

• H10P74/238

  comprising acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection or in-situ thickness measurement · CPC title

• H10P70/234

  the processing being the formation of vias or contact holes · CPC title

• H10P14/6536

  by exposure to radiation, e.g. visible light · CPC title

• H10P14/6342

  Liquid deposition, e.g. spin-coating, sol-gel techniques or spray coating · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title