Methods of forming dislocation enhanced strain in NMOS structures

Patent metadata

Field	Value
Publication number	US-10396201-B2
Application number	US-201314912594-A
Country	US
Kind code	B2
Filing date	Sep 26, 2013
Priority date	Sep 26, 2013
Publication date	Aug 27, 2019
Grant date	Aug 27, 2019

Abstract

Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods and structures may include forming a thin silicon germanium material in a source/drain opening of a device comprising silicon, wherein multiple dislocations are formed in the silicon germanium material. A source/drain material may be formed on the thin silicon germanium material, wherein the dislocations induce a tensile strain in a channel region of the device.

First claim

What is claimed is:

1. A method of forming a structure comprising:
forming openings in source/drain regions of a device disposed on a substrate, the openings beneath dielectric spacers adjacent to a gate electrode, wherein the gate electrode is on a gate dielectric, and wherein the openings further extend beneath the gate dielectric;
forming a dislocation nucleation material in the source/drain openings, wherein the dislocation nucleation material is selectively grown using epitaxial growth, wherein the dislocation nucleation material comprises a lattice constant that is mismatched with a substrate lattice constant, and wherein a plurality of dislocations form in the dislocation nucleation material, and wherein the dislocation nucleation material is in contact with a bottom surface of the dielectric spacers and with a bottom surface of the gate dielectric; and
forming a source/drain material on the dislocation nucleation material, wherein a plurality of source/drain dislocations are formed in the source/drain material.

2. The method of claim 1 further comprising wherein a channel region remains underneath a gate electrode of the device, and wherein the channel region is not removed during the opening formation process.

3. The method of claim 1 further comprising wherein the dislocation nucleation material induces a tensile stress in the source/drain material, and wherein the device comprises one of a trigate, a finFET and a nanowire structure.

4. The method of claim 1 further comprising wherein the dislocation nucleation material comprises a silicon germanium material.

5. The method of claim 4 wherein the plurality of dislocations formed in the silicon germanium material produce a tensile strain in the source/drain material that induces a tensile strain in a channel region adjacent the source/drain material.

6. The method of claim 1 further comprising wherein the source/drain material comprises a silicon phosphorus material, and wherein the source/drain material is selectively grown on a silicon portion of the substrate.

7. The method of claim 4 further comprising wherein the amount of germanium in the silicon germanium material comprises a range of about 40 percent to about 80 percent by weight.

8. The method of claim 7 further comprising wherein the dislocation nucleation material further comprises at least one of phosphorus and arsenic.

9. The method of claim 4 further comprising wherein the silicon germanium comprises a continuous distribution of arsenic and phosphorus.

10. The method of claim 1 further comprising wherein the dislocation material comprises a lower portion comprising silicon germanium, phosphorus and arsenic and an upper portion comprising silicon and phosphorus.

11. A method of forming a structure comprising:
forming a silicon germanium material on a source/drain opening of a device comprising silicon, wherein multiple dislocations are formed in the silicon germanium material, wherein the silicon germanium material having the multiple dislocations therein is selectively grown using epitaxial growth, the source/drain opening beneath a dielectric spacer adjacent to a gate electrode, wherein the gate electrode is on a gate dielectric, wherein the opening further extends beneath the gate dielectric, and wherein the silicon germanium material is in contact with a bottom surface of the dielectric spacer and with a bottom surface of the gate dielectric; and
forming a source/drain material on the silicon germanium material, wherein the dislocations induce source/drain dislocations throughout the source/drain material.

12. The method of claim 11 further comprising wherein overlapping strain fields in the source/drain material impart a tensile strain to a channel region of the device adjacent the source/drain material.

13. The method of claim 12 further comprising wherein the source/drain material comprises a lattice constant that is mismatched with the lattice constant of the substrate.

14. The method of claim 11 further comprising wherein the structure comprises a portion of an NMOS structure.

Assignees

• Intel Corp

Inventors

• Jackson Michael
• Murthy Anand
• Glass Glenn
• Morarka Saurabh
• Mohapatra Chandra

Classifications

• H01L29/66636

  Electricity · mapped topic

• H01L29/165

  Electricity · mapped topic

• H01L29/66568

  Electricity · mapped topic

• H01L29/0673

  Electricity · mapped topic

• H01L29/1054

  Electricity · mapped topic