Semiconductor device

Patent metadata

Field	Value
Publication number	US-10396189-B2
Application number	US-201815987912-A
Country	US
Kind code	B2
Filing date	May 24, 2018
Priority date	May 30, 2017
Publication date	Aug 27, 2019
Grant date	Aug 27, 2019

Abstract

Considering ease of electrical conduction tests and the like, electrodes provided mainly above an active region are desirably continuous on a single plane. A semiconductor device is provided, including: a semiconductor substrate; a first top surface electrode and a second top surface electrode that are provided above a top surface of the semiconductor substrate and contain a metal material; and a first connecting portion that electrically connects to the first top surface electrode and contains a semiconductor material, wherein the second top surface electrode has: a first region and a second region that are arranged being separated from each other with the first connecting portion as a boundary in a top view of the semiconductor substrate, and a second connecting portion that connects the first region and the second region above the first connecting portion.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor substrate;
a first top surface electrode and a second top surface electrode that are provided above a top surface of the semiconductor substrate and contain a metal material; and
a first connecting portion that electrically connects to the first top surface electrode and contains a semiconductor material, wherein
the second top surface electrode has:
a first region and a second region that are arranged being separated from each other with the first connecting portion as a boundary in a top view of the semiconductor substrate, and
a second connecting portion that connects the first region and the second region above the first connecting portion.

2. The semiconductor device according to claim 1 , wherein the first connecting portion has a gate bridge trench portion that: is provided spreading from the top surface of the semiconductor substrate and reaching a predetermined depth; is positioned below the second connecting portion; and electrically connects with the first top surface electrode.

3. The semiconductor device according to claim 2 , wherein
the first top surface electrode has a metallic wiring layer separated at least at a position of the second connecting portion in a top view of the semiconductor substrate, and
the metallic wiring layer electrically connects to the gate bridge trench portion.

4. The semiconductor device according to claim 2 , further comprising a first trench portion that electrically connects with the first top surface electrode and a second trench portion that electrically connects with the second top surface electrode, the first trench portion and the second trench portion each being provided at a predetermined depth position from the top surface of the semiconductor substrate, wherein
a width of the gate bridge trench portion in a second direction perpendicular to a first direction which is a direction of extension of the first connecting portion in a top view of the semiconductor substrate is larger than both a width of the second trench portion in the first direction and a width of the first trench portion in the first direction.

5. The semiconductor device according to claim 2 , wherein the first connecting portion has a plurality of the gate bridge trench portions provided being separated from each other in a second direction perpendicular to a first direction which is a direction of extension of the first connecting portion in a top view of the semiconductor substrate.

6. The semiconductor device according to claim 2 , wherein the first connecting portion has the gate bridge trench portion provided annularly in a top view of the semiconductor substrate.

7. The semiconductor device according to claim 1 , wherein
the first connecting portion is a polysilicon wiring layer provided above the top surface of the semiconductor substrate, and
the polysilicon wiring layer is provided also below the second connecting portion.

8. The semiconductor device according to claim 1 , wherein
the first top surface electrode is a gate metal layer, and
the second top surface electrode is an emitter electrode.

9. The semiconductor device according to claim 1 , wherein
the semiconductor device has an active region including a transistor region and a free wheeling diode region, and
the second connecting portion connects the first region and the second region between at least two of the free wheeling diode regions that are detached from each other in a second direction perpendicular to a first direction which is a direction of extension of the first connecting portion in a top view of the semiconductor substrate.

10. The semiconductor device according to claim 9 , wherein a width of the second connecting portion in the first direction is smaller than a width of one of the free wheeling diode regions in the first direction.

11. The semiconductor device according to claim 9 , wherein the second connecting portion that connects the first region and the second region is not provided between at least two of the free wheeling diode regions among a plurality of the free wheeling diode regions detached from each other in the second direction.

12. The semiconductor device according to claim 9 , wherein
the semiconductor substrate has a top surface killer region that: is provided in a predetermined depth range from the top surface between the free wheeling diode regions detached from each other in the second direction; and adjusts hole lifetime, and
a width of the top surface killer region in the first direction in a region not provided with the second connecting portion is larger than a width of the top surface killer region in the first direction in a region provided with the second connecting portion.

13. The semiconductor device according to claim 9 , wherein the second connecting portion is provided at least between two of the free wheeling diode regions arranged close to a middle portion of the semiconductor substrate in a top view of the semiconductor substrate.

14. The semiconductor device according to claim 13 , wherein a width, in the first direction, of the second connecting portion provided between two of the free wheeling diode regions arranged close to a middle portion of the semiconductor substrate in a top view of the semiconductor substrate is larger than a width, in the first direction, of the second connecting portion provided between two of the free wheeling diode regions arranged away from the middle portion of the semiconductor substrate in a top view of the semiconductor substrate.

15. The semiconductor device according to claim 1 , wherein
the semiconductor device has an active region including a transistor region and a free wheeling diode region,
in the active region, the first top surface electrode electrically connects with a first trench portion in the transistor region, and
the semiconductor device further comprises a third top surface electrode that: is provided, in the active region, being detached from the first top surface electrode and the second top surface electrode, and electrically connects with a second trench portion in the transistor region.

16. The semiconductor device according to claim 15 , wherein the semiconductor substrate has a dummy bridge trench portion that: is provided spreading from the top surface of the semiconductor substrate and reaching a predetermined depth; is positioned below the second connecting portion; and electrically connects with the third top surface electrode.

17. The semiconductor device according to claim 15 , wherein the first connecting portion has a gate bridge trench portion that: is provided spreading from the top surface of the semiconductor substrate and reaching a predetermined depth; is positioned below the third top surface electrode; and electrically connects with the first top surface electrode.

18. The semiconductor device according to claim 17 , wherein the gate bridge trench portion electrically connects:
a periphery portion of the first top surface electrode that: is provided near an end portion of an active region of the semiconductor substrate; and extends in a second direction perpendicular to a first direction which is a direction of extension of the first connecting portion; and
an extending portion of the first top surface electrode that extends in the first direction between a pair of the periphery portions.

19. The semiconductor device according to claim 1 , wherein
the semiconductor device has:
a first trench portion that: is provided at a p

Assignees

• Fuji Electric Co Ltd

Inventors

• Naito Tatsuya

Classifications

• H10D64/01346

  in a gaseous ambient using an oxygen or a water vapour, e.g. oxidation through a layer (H10D64/01344 takes precedence) · CPC title

• H10D64/01344

  in a nitrogen-containing ambient, e.g. N2O oxidation · CPC title

• H10P95/405

  using cavities formed by hydrogen or noble gas ion implantation · CPC title

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P74/273

  Interconnections for measuring or testing, e.g. probe pads · CPC title