Semiconductor device

Patent metadata

Field	Value
Publication number	US-9991353-B2
Application number	US-201615333193-A
Country	US
Kind code	B2
Filing date	Oct 25, 2016
Priority date	Dec 3, 2015
Publication date	Jun 5, 2018
Grant date	Jun 5, 2018

Abstract

Machining accuracy of an IGBT region is worsened due to a height difference caused by polysilicon. Therefore, there is a problem that characteristic variation of the IGBT increases. Provided is a semiconductor device including a semiconductor substrate; a gate wiring layer provided on a front surface side of the semiconductor substrate; and a gate structure that includes a gate electrode and is provided on the front surface of the semiconductor substrate. The gate wiring layer includes an outer periphery portion that is a metal wiring layer and is provided along an outer periphery of the semiconductor substrate; and an extending portion that is a metal wiring layer, is provided extending from the outer periphery portion toward a central portion of the semiconductor substrate, and is electrically connected to the gate electrode.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor substrate;
a gate wiring layer provided on a front surface side of the semiconductor substrate;
a gate structure that includes a gate electrode and is provided on the front surface of the semiconductor substrate,
a plurality of element regions that each have the gate structure; and
a gate trench portion extending from one of the element regions to another of the element regions, wherein
the gate wiring layer includes:
an outer periphery portion that is a metal wiring layer and is provided along an outer periphery of the semiconductor substrate;
an extending portion that is a metal wiring layer, is provided extending from the outer periphery portion toward a central portion of the semiconductor substrate, and is electrically connected to the gate electrode,
the extending portion of the gate wiring layer extends in a first direction from the outer periphery portion toward the central portion between two of the element regions,
the gate trench portion extends in a second direction that is orthogonal to the first direction,
the gate electrode is embedded entirely in the gate trench portion, and
the gate wiring layer is electrically connected to the gate electrode on top of the gate trench portion between the element regions.

2. The semiconductor device according to claim 1 , further comprising:
a dummy trench portion that extends in the second direction, wherein
the dummy trench portion extends at least to a second-direction end of the element regions.

3. The semiconductor device according to claim 2 , wherein
the dummy trench portion crosses the gate wiring layer below the gate wiring layer extending in the first direction between the two element regions.

4. The semiconductor device according to claim 1 , wherein
the extending portion of the gate wiring layer is provided extending from one side of the outer periphery portion to another side of the periphery portion that is opposite the one side.

5. The semiconductor device according to claim 1 , further comprising:
an emitter electrode provided on top of the gate structure, wherein
the emitter electrode is distanced from the gate wiring layer and divided into a plurality of pieces.

6. The semiconductor device according to claim 5 , further comprising:
a protective film that is provided on top of the gate wiring layer; and
a metal layer that is electrically separated from the gate wiring layer by the protective film and is electrically connected to a plurality of the emitter electrodes on top of the plurality of emitter electrodes.

7. The semiconductor device according to claim 1 , further comprising: an interlayer insulating film that is provided in direct contact with the front surface of the semiconductor substrate, and an emitter electrode that is provided in contact with an upper surface of the interlayer insulating film, wherein the emitter electrode is formed to cover a plurality of gate trench portions, and in a region outside of the gate trench portion and a dummy trench portion, the semiconductor substrate and the interlayer insulating film are directly connected to each other and the interlayer insulating film directly contacts the gate wiring layer.

8. The semiconductor device according to claim 7 , further comprising:
a well region that is provided on the front surface of the semiconductor substrate directly beneath the gate wiring layer in the extending portion, the well region being deeper than the plurality of gate trench portions and the dummy trench portion.

9. A semiconductor device comprising:
a semiconductor substrate;
a gate wiring layer provided on a front surface side of the semiconductor sub state;
a gate structure that includes a gate electrode and is provided on the front surface of the semiconductor substrate,
a plurality of element regions that each have the gate structure; and
a gate trench portion extending from one of the element regions to another of the element regions, wherein
the gate wiring layer includes:
an outer periphery portion that is a metal wiring layer and is provided along an outer periphery of the semiconductor substrate;
an extending portion that is a metal wiring layer, is provided extending from the outer periphery portion toward a central portion of the semiconductor substrate, and is electrically connected to the gate electrode,
the extending portion of the gate wiring layer extends in a first direction from the outer periphery portion toward the central portion between two of the element regions,
the gate trench portion extends in a second direction that is orthogonal to the first direction,
the gate electrode is embedded in the gate trench portion,
the gate wiring layer is electrically connected to the gate electrode on top of the gate trench portion between the element regions,
the gate trench portion is provided with a U shape whose long direction is parallel to the second direction, and a short direction of the U shape extends in the first direction below the gate wiring layer, and
the gate wiring layer is directly connected to the gate electrode in the gate trench portion in the short direction.

10. A semiconductor device comprising:
a semiconductor substrate;
a gate wiring layer provided on a front surface side of the semiconductor substrate:
a gate structure that includes a gate electrode and is provided on the front surface of the semiconductor substrate,
a plurality of element regions that each have the gate structure; and
a gate trench portion extending from one of the element regions to another of the element regions, wherein
the gate wiring layer includes:
an outer periphery portion that is a metal wiring layer and is provided along an outer periphery of the semiconductor substrate;
an extending portion that is a metal wiring layer, is provided extending from the outer periphery portion toward a central portion of the semiconductor substrate, and is electrically connected to the gate electrode,
the extending portion of the gate wiring layer extends in a first direction from the outer periphery portion toward the central portion between two of the element regions,
the gate trench portion extends in a second direction that is orthogonal to the first direction,
the gate electrode is embedded in the gate trench portion,
the gate wiring layer is electrically connected to the gate electrode on top of the gate trench portion between the element regions,
the gate trench portion also extends in the first direction below the extending portion of the gate wiring layer,
the gate wiring layer is directly connected to the gate electrode of the gate trench portion extending in the first direction, and
the gate trench portion is provided with a lattice shape formed by intersections of portions extending in the first direction and portions extending in the second direction.

11. The semiconductor device according to claim 9 , further comprising:
a dummy trench portion that extends in the second direction, wherein
the dummy trench portion extends at least to a second-direction end of the element regions, and
an interlayer insulating film that is provided between the semiconductor substrate and the gate wiring layer, wherein
in a region outside of the gate trench portion and the dummy trench portion, the semiconductor substrate and the interlayer insulating film are directly connected to each other and the interlayer insulating film directly contacts the gate wiring layer.

Assignees

• Fuji Electric Co Ltd

Inventors

• Naito Tatsuya

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H01L29/4236

  Electricity · mapped topic

• H01L23/528

  Electricity · mapped topic

• H01L29/41708

  Electricity · mapped topic

• H01L29/7397

  Electricity · mapped topic