Nanogaps on atomically thin materials as non-volatile read/writable memory devices

Patent metadata

Field	Value
Publication number	US-10396175-B2
Application number	US-201514952433-A
Country	US
Kind code	B2
Filing date	Nov 25, 2015
Priority date	Nov 25, 2014
Publication date	Aug 27, 2019
Grant date	Aug 27, 2019

Abstract

The present invention relates to the presence of nanogaps across a metal dispersed over an atomically-thin material, such that the nanogap exposes the atomically-thin material. The resulting device offers an ultra-short gap with ballistic transport and demonstrated switching in the presence of a gate or dielectric material in close proximity to the channel.

First claim

What is claimed:

1. A non-volatile memory element, comprising an atomically-thin layer on top of a gate layer which is on top of a substrate, and a metallic layer with a bowtie geometry dispersed on top of the atomically-thin layer, wherein an electromigrated break junction in the metallic layer at the bowtie geometry provides well defined metallic interfaces and a clean nanogap channel of a width of about 0.1 nm to 10 nm entirely across the metallic layer that exposes the top of the atomically thin layer, such that the electromigrated break junction divides the metallic layer into a source electrode and a drain electrode that are separated by the clean nanogap, wherein the exposed atomically-thin layer functions as an ultra-short ballistic channel between the source and drain electrodes through the atomically thin layer over the gate layer and the substrate, and further wherein the substrate comprises an insulating material that supports charge trapping or a floating gate electrode.

2. The non-volatile memory element of claim 1 , further comprising a dielectric layer between the gate layer and the atomically thin layer, wherein the dielectric material is selected from the group consisting of SiO 2 , BN, Al 2 O 3 , and other similar insulating materials.

3. The non-volatile memory element of claim 2 , wherein a floating gate is embedded in the dielectric layer.

4. The non-volatile memory element of claim 1 , wherein the atomically thin layer comprises graphene, transition metal dichalcogenides, black phosphorous, or similar laminar or nanotube material.

5. The non-volatile memory element of claim 4 , wherein the atomically-thin or nanotube material comprises a single layer.

6. The non-volatile memory element of claim 4 , wherein the atomically-thin or nanotube material comprises two or more layers.

7. The non-volatile memory element of claim 1 , wherein the gate layer is on top of a substrate.

8. The non-volatile memory element of claim 1 , wherein the gate layer comprises a material selected from the group consisting of a metals, silicon, and graphene.

9. The non-volatile memory element of claim 1 , wherein the metallic layer comprises a material that can be electromigrated, such as Au, Pd, Ag, Pt, Ni.

10. The non-volatile memory element of claim 1 , wherein the metallic layer has a narrow constriction on the atomically-thin layer.

11. A non-volatile memory element, comprising an atomically-thin layer on top of a gate layer which is on top of a substrate, and a metallic layer with a bowtie geometry dispersed on top of the atomically-thin layer, wherein an electromigrated break junction in the metallic layer at the bowtie geometry provides well defined metallic interfaces and a clean nanogap channel of a width of about 0.1 nm to 10 nm entirely across the metallic layer that exposes the top of the atomically thin layer, such that the electromigrated break junction divides the metallic layer into a source electrode and a drain electrode that are separated by the clean nanogap, wherein the exposed atomically-thin layer functions as an ultra-short ballistic channel between the source and drain electrodes through the atomically thin layer over the gate layer and the substrate, and further wherein the atomically-thin layer comprises two or more layers.

12. The non-volatile memory element of claim 11 , further comprising a dielectric layer between the gate layer and the atomically thin layer, wherein the dielectric material is selected from the group consisting of SiO 2 , BN, Al 2 O 3 , and other similar insulating materials.

13. The non-volatile memory element of claim 12 , wherein a floating gate is embedded in the dielectric layer.

14. The non-volatile memory element of claim 11 , wherein the atomically thin layer comprises graphene, transition metal dichalcogenides, black phosphorous, or similar laminar or nanotube material.

15. The non-volatile memory element of claim 11 , wherein the gate layer is on top of a substrate.

16. The non-volatile memory element of claim 11 , wherein the gate layer comprises a material selected from the group consisting of a metals, silicon, and graphene.

17. The non-volatile memory element of claim 11 , wherein the substrate comprises an insulating material that supports charge trapping or a floating gate electrode.

18. The non-volatile memory element of claim 11 , wherein the metallic layer comprises a material that can be electromigrated, such as Au, Pd, Ag, Pt, Ni.

19. The non-volatile memory element of claim 11 , wherein the metallic layer has a narrow constriction on the atomically-thin layer.

Assignees

• Strachan Douglas Robert
• Sundararajan Abhishek
• Boland Mathias Joseph
• Univ Kentucky Res Found

Inventors

• Strachan Douglas Robert
• Sundararajan Abhishek
• Boland Mathias Joseph

Classifications

• H01L29/24

  Electricity · mapped topic

• H01L29/66484 Primary

  Electricity · mapped topic

• H01L29/42324

  Electricity · mapped topic

• H01L29/778

  Electricity · mapped topic

• H01L29/66825

  Electricity · mapped topic