Integrated circuit package substrate

Patent metadata

Field	Value
Publication number	US-10390438-B2
Application number	US-201715821532-A
Country	US
Kind code	B2
Filing date	Nov 22, 2017
Priority date	Apr 25, 2013
Publication date	Aug 20, 2019
Grant date	Aug 20, 2019

Abstract

Embodiments of the present disclosure are directed towards techniques and configurations for dual surface finish package substrate assemblies. In one embodiment a method includes depositing a first surface finish on one or more electrical routing features located on a first side of a package substrate and on one or more lands located on a second side of the package substrate, the second side being opposite the first side of the substrate. The method may further include removing the first surface finish on the first side of the package substrate; and depositing a second surface finish on the one or more electrical routing features of the first side. The depositing of the second surface finish may be accomplished by one of a Direct Immersion Gold (DIG) process or an Organic Solderability Preservative (OSP) process. Other embodiments may be described and/or claimed.

First claim

What is claimed is:

1. A method of forming an integrated circuit (IC) package substrate comprising:
providing a package substrate having a first side and a second side opposite the first side, the package substrate including a first dielectric layer forming the first side, and a second dielectric layer forming the second side, a central core comprising one or more dies being disposed between the first dielectric layer and the second dielectric layer;
depositing a first surface finish on one or more electrical routing features disposed on the first side of a package substrate and on one or more lands disposed on the second side, the first dielectric layer comprising an outer surface of the first side of the package substrate, wherein the one or more electrical routing features are further disposed in, and extend through, the first dielectric layer of the first side, wherein the one or more electrical routing features have an outer surface that is coplanar with the outer surface of the first dielectric layer;
removing the first surface finish from the first side of the package substrate, the first surface finish remaining on the one or more lands of the second side; and
depositing a second surface finish on and in direct contact with the outer surface of the one or more electrical routing features on the first side of the package substrate, and on the first surface finish remaining on one or more lands of the second side,
wherein the one or more electrical routing features have a pitch to bond with die interconnect structures of the one or more dies, wherein the second surface finish has a different chemical composition than the first surface finish, wherein a bump pitch of the electrical routing features is 50 micrometers, and wherein the electrical routing features include a pad size of 49 micrometers.

2. The method of claim 1 , wherein the depositing of the second surface finish is accomplished by a Direct Immersion Gold (DIG) process.

3. The method of claim 1 , wherein the depositing of the second surface finish is accomplished by an Organic Solderability Preservative (OSP) process.

4. The method of claim 1 , wherein the depositing of the first surface finish on one or more electrical routing features and one or more lands occurs simultaneously using a plating process.

5. The method of claim 1 , wherein a planarizing process is used, at least in part, in removing the first surface finish on the first side.

6. The method of claim 1 , further comprising forming the electrical routing features using a method comprising:
laminating a dielectric material over a metal conductor to form a dielectric layer;
selectively removing, by a laser, dielectric material to form voids in the dielectric layer revealing the metal conductor;
plating a fill metal into the voids created by the laser; and
planarizing the fill metal to a level even with a surface of the dielectric layer.

7. The method of claim 1 , wherein depositing the first surface finish is performed using an electroless plating process.

8. The method of claim 1 , wherein depositing the first surface finish comprises depositing nickel (Ni).

9. The method of claim 8 , wherein depositing the first surface finish further comprises depositing one or both of palladium or gold.

10. The method of claim 9 , wherein depositing the first surface finish comprises depositing gold using an electroless nickel-immersion gold (ENIG+EG) process.

Assignees

• Intel Corp

Inventors

• Zhang Qinglei

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/252

  comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title

• H10W72/072

  of bump connectors · CPC title