Semiconductor device having a memory cell and method of forming the same

Patent metadata

Field	Value
Publication number	US-10388657-B2
Application number	US-201715619323-A
Country	US
Kind code	B2
Filing date	Jun 9, 2017
Priority date	Sep 18, 2014
Publication date	Aug 20, 2019
Grant date	Aug 20, 2019

Abstract

There is provided an apparatus includes a substrate having a main surface, a wordline buried in the substrate and a bitline buried in a shallower area than the wordline in the substrate.

First claim

I claim:

1. A device comprising:
an active region of semiconductor material, the active region being defined by a trench isolation structure;
a first diffusion region in the active region, the first diffusion region including a top surface and a bottom surface;
a second diffusion region in the active region, the second diffusion region having an overall width and including an uppermost surface that extends at a single elevation across the overall width, and having a bottom surface;
a buried wordline in the active region, the buried wordline defining a channel region between the first and second diffusion regions;
a trench in the active region, the trench defining the uppermost surface of the second diffusion region such that the uppermost surface of the second diffusion region is dented more than the top surface of the first diffusion region toward the buried wordline, the trench including a lower portion and an upper portion over the lower portion;
a buried bitline filling the lower portion of the trench, the buried bitline having an upper surface disposed elevationally below the top surface of the first diffusion region, the buried bitline being in an electrical contact with the second diffusion region and keeping the upper portion of the trench unfilled; and
dielectric material filling the upper portion of the trench.

2. The device of claim 1 , wherein the active region includes a top surface, the top surface of the active region being substantially coplanar with the top surface of the first diffusion region.

3. The device of claim 1 , wherein the bottom surface of the first diffusion region being at substantially the same level as the bottom surface of the second diffusion region.

4. The device of claim 1 , wherein the buried wordline defines the channel region between the bottom surfaces of the first and second diffusion regions.

5. The device of claim 1 , wherein each of the trench and the buried bitline has a snake shape pattern and extends in a first direction that is substantially orthogonal to a second direction in which the buried wordline extends.

6. The device of claim 1 , wherein each of the trench and the buried bitline has a straight shape pattern and extends in a first direction that is substantially orthogonal to a second direction in which the buried wordline extends.

7. The device of claim 1 , further comprising a buried bitline spacer between the buried bitline and the lower portion of the trench.

8. The device of claim 7 , wherein the buried bitline spacer comprises an insulating film.

9. The device of claim 1 , further comprising a memory element over the active region, the memory element being in electrical contact with the first diffusion region.

10. The device of claim 9 , wherein the memory element comprises a capacitor.

11. A device comprising:
an active region of semiconductor material, the active region being defined by a trench isolation structure;
a first diffusion region in the active region, the first diffusion region including a top surface and a bottom surface;
a second diffusion region in the active region, the second diffusion region including an uppermost surface and a bottom surface;
a buried wordline in the active region, the buried wordline defining a channel region between the first and second diffusion regions;
a trench in the active region, the trench defining the uppermost surface of the second diffusion region such that the uppermost surface of the second diffusion region is recessed more than the top surface of the first diffusion region toward the buried wordline, the trench including a lower portion and an upper portion over the lower portion;
a buried bitline filling the lower portion of the trench, the buried bitline having an upper surface disposed elevationally below the top surface of the first diffusion region, the buried bitline being in an electrical contact with the second diffusion region and keeping the upper portion of the trench unfilled;
dielectric material filling the upper portion of the trench;
a buried bitline spacer between the buried bitline and the lower portion of the trench; and
wherein the buried bitline spacer comprises an air gap.

12. A device comprising:
an active region of semiconductor material, the active region being defined by a trench isolation structure;
a first diffusion region in the active region, the first diffusion region including a top surface and a bottom surface;
a second diffusion region in the active region, the second diffusion region including an uppermost surface and a bottom surface;
a buried wordline in the active region, the buried wordline defining a channel region between the first and second diffusion regions;
a trench in the active region, the trench defining the uppermost surface of the second diffusion region such that the uppermost surface of the second diffusion region is dented more than the top surface of the first diffusion region toward the buried wordline, the trench including a lower portion and an upper portion over the lower portion;
a buried bitline filling the lower portion of the trench, the buried bitline having an upper surface disposed elevationally below the top surface of the first diffusion region, the buried bitline being in an electrical contact with the second diffusion region and keeping the upper portion of the trench unfilled;
dielectric material filling the upper portion of the trench;
a buried bitline spacer between the buried bitline and the lower portion of the trench; and
wherein the buried bitline includes a top surface and the buried bitline spacer includes a top surface, the top surface of buried bitline being substantially coplanar with the top surface of the buried bitline spacer.

13. A device comprising:
an active region of semiconductor material;
a first trench formed in the active region, the first trench including a lower portion and an upper portion over the lower portion;
a buried wordline formed in the lower portion of the first trench, the buried wordline defining a channel region in the active region along the lower portion of the first trench, the channel region having a first end and a second end, and the buried wordline including a top surface at a boundary between the lower and upper portions of the first trench;
first cap dielectric material filling the upper portion of the first trench;
a second trench formed in the active region in a depth that is shallower than the top surface of the buried wordline, the second trench including a lower portion and an upper portion over the bottom portion;
a buried bitline formed in the lower portion of the second trench;
second cap dielectric material filling the upper portion of the second trench;
a first diffusion region formed in the active region to couple with the first end of the channel region, the buried bitline having an upper surface disposed elevationally below an upper surface of the first diffusion region; and
a second diffusion region formed in the active region to couple with the second end of the channel region, the second diffusion region being in electrical contact with the bitline and being disposed entirely beneath the bitline.

14. The device of claim 13 , further comprising:
a third trench formed in the active region in a depth that is substantially the same as the first trench, the third trench including a lower portion and an upper portion over the lower portion;
an additional buried wordline formed in the lower portion of the third trench, the additional buried wordline defining an additional channel region in the active region along the lower portion of the third trench, and the add

Assignees

• Micron Technology Inc

Inventors

• Wu Nan

Classifications

• H01L27/10814 Primary

  Electricity · mapped topic

• H01L27/10876

  Electricity · mapped topic

• H01L27/10885

  Electricity · mapped topic

• H01L27/0207

  Electricity · mapped topic

• H10D89/10

  Integrated device layouts · CPC title