Composite contact etch stop layer

Patent metadata

Field	Value
Publication number	US-10388562-B2
Application number	US-201715678229-A
Country	US
Kind code	B2
Filing date	Aug 16, 2017
Priority date	Aug 16, 2017
Publication date	Aug 20, 2019
Grant date	Aug 20, 2019

Abstract

A composite etch stop layer includes an oxide layer formed over a sacrificial gate structure and a nitride layer formed over the oxide layer. The oxide layer is disposed over only lower portions of the sacrificial gate structure while the nitride layer envelops the oxide layer and is disposed directly over a top surface of the sacrificial gate structure. Sensitivity of the nitride layer to oxidation, such as during the formation of an interlayer dielectric over the composite etch stop layer, is decreased by eliminating the oxide layer from upper portions of the sacrificial gate layer.

First claim

What is claimed is:

1. A method of fabricating a device, comprising:
forming a sacrificial gate structure over a semiconductor substrate, wherein the sacrificial gate structure includes a sacrificial gate and a sacrificial gate cap formed over a top surface of the sacrificial gate;
forming a sidewall spacer layer over sidewalls of the sacrificial gate structure;
forming a first etch stop layer over the sidewall spacer layer laterally adjacent to the sacrificial gate;
removing portions of the first etch stop layer from over a top surface of the sacrificial gate cap and from over surfaces of the sidewall spacer layer laterally adjacent to the sacrificial gate cap; and
forming a second etch stop layer over the first etch stop layer, the surfaces of the sidewall spacer layer laterally adjacent to the sacrificial gate cap, and the sacrificial gate cap, wherein the second etch stop layer is formed directly on the sacrificial gate cap and the surfaces of the sidewall spacer layer laterally adjacent to the sacrificial gate cap without intervening layers.

2. The method of claim 1 , wherein the first and second etch stop layers are formed by atomic layer deposition.

3. The method of claim 1 , wherein the first etch stop layer comprises silicon dioxide and the second etch stop layer comprises silicon nitride.

4. The method of claim 1 , wherein a top surface of the first etch stop layer is coplanar with the top surface of the sacrificial gate.

5. The method of claim 1 , wherein the second etch stop layer is formed directly over the first etch stop layer laterally adjacent to the sacrificial gate.

6. The method of claim 1 , wherein forming the sacrificial gate structure comprises forming a plurality of sacrificial gate structures over the semiconductor substrate.

7. The method of claim 6 , further comprising forming a source/drain junction over the semiconductor substrate between adjacent sacrificial gate structures.

8. The method of claim 7 , wherein the first etch stop layer is formed directly over the source/drain junction.

9. A method of fabricating a device, comprising:
forming a plurality of sacrificial gate structures over a semiconductor substrate, wherein the sacrificial gate structures each include a sacrificial gate and a sacrificial gate cap formed over a top surface of the sacrificial gate;
forming a sidewall spacer layer over sidewalls of the sacrificial gate structures;
forming a first etch stop layer over the sidewall spacer layer and over a top surface of the sacrificial gate caps;
forming a hard mask over the first etch stop layer;
etching the hard mask to expose the first etch stop layer over the top surface of the sacrificial gate caps and recess the hard mask between adjacent sacrificial gate structures;
removing exposed portions of the first etch stop layer from over the top surface of the sacrificial gate caps and from over surfaces of the sidewall spacer layer laterally adjacent to the sacrificial gate caps;
removing remaining portions of the hard mask from between the adjacent sacrificial gate structures; and
forming a second etch stop layer over the first etch stop layer and directly over the sacrificial gate caps.

10. The method of claim 9 , wherein the first etch stop layer comprises silicon dioxide and the second etch stop layer comprises silicon nitride.

11. The method of claim 9 , wherein the hard mask comprises a spin on hard mask.

12. The method of claim 9 , further comprising planarizing the hard mask prior to recessing the hard mask between the adjacent sacrificial gate structures.

13. The method of claim 9 , wherein a top surface of the first etch stop layer is coplanar with the top surface of the sacrificial gate.

14. The method of claim 9 , wherein the second etch stop layer is formed directly over the sidewall spacer layer laterally adjacent to the sacrificial gate caps.

15. The method of claim 9 , wherein the second etch stop layer is formed directly over the first etch stop layer laterally adjacent to the sacrificial gate and directly over the sidewall spacer layer laterally adjacent to the sacrificial gate caps.

16. The method of claim 9 , further comprising forming a source/drain junction over the semiconductor substrate between the adjacent sacrificial gate structures.

17. The method of claim 16 , wherein the first etch stop layer is formed directly over the source/drain junction.

18. The method of claim 9 , further comprising a plurality of fins from the semiconductor substrate and forming the plurality of sacrificial gate structures over the plurality of fins.

Assignees

• Globalfoundries Inc

Inventors

• Huang Haigou
• Jaeger Daniel
• Wu Xusheng
• Gao Jinsheng

Classifications

• H10P14/69433

  the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title