Non-volatile random access memory with gated security access

Patent metadata

Field	Value
Publication number	US-10387333-B2
Application number	US-201715399625-A
Country	US
Kind code	B2
Filing date	Jan 5, 2017
Priority date	Jan 5, 2017
Publication date	Aug 20, 2019
Grant date	Aug 20, 2019

Abstract

Systems and methods are disclosed for providing secure access to a non-volatile random access memory. One such method comprises sending an unlock password to a non-volatile random access memory (NVRAM) in response to a trusted boot program executing on a system on chip (SoC). The NVRAM compares the unlock password to a pass gate value provisioned in the NVRAM. If the unlock password matches the pass gate value, a pass gate is unlocked to enable the SoC to access a non-volatile cell array in the NVRAM.

First claim

What is claimed is:

1. A method for providing secure access to a non-volatile random access memory, the method comprising:
in response to a trusted boot program executing on a system on chip (SoC), sending an unlock password from the SoC to a non-volatile random access memory (NVRAM) coupled to the SoC;
the NVRAM comparing the unlock password to a pass gate value provisioned in the NVRAM; and
if the unlock password matches the pass gate value unlocking a pass gate within the NVRAM to enable the SoC to access a non-volatile cell array in the NVRAM,
wherein, when the NVRAM is powered down, the pass gate is configured in a locked state preventing access to the NVRAM.

2. The method of claim 1 , wherein the pass gate value is fetched from a programmable memory cell.

3. The method of claim 1 , wherein the pass gate value is stored in a NVRAM fuse.

4. The method of claim 1 , wherein the pass gate value is hardcoded into a memory device using one or more of a plurality of logic circuits, a read only memory, and metal traces.

5. The method of claim 1 , wherein the pass gate comprises one or more switches for electrically coupling a random access memory (RAM) controller residing on the SoC to the non-volatile cell array.

6. The method of claim 1 , wherein the unlock password comprises an encrypted message, and the NVRAM comparing the unlock password to the pass gate value provisioned in the NVRAM comprises decrypting an encrypted message comprising the unlock password.

7. The method of claim 1 , further comprising:
if the unlock password does not match the pass gate value, maintain the pass gate in a locked state.

8. The method of claim 1 , further comprising:
maintaining a self-destruct counter to keep track of a number of failed password exchanges between the SoC and the NVRAM; and
if the self-destruct counter exceeds a threshold, permanently lock the pass gate.

9. A system for providing secure access to a non-volatile random access memory, the method comprising:
means for sending from a system on chip (SoC) an unlock password to a non-volatile random access memory (NVRAM) coupled to the SoC in response to a trusted boot program executing on the SoC;
means for comparing the unlock password to a pass gate value provisioned in the NVRAM; and
means for unlocking a pass gate within the NVRAM if the unlock password matches the pass gate value to enable the SoC to access a non-volatile cell array in the NVRAM,
wherein, when the NVRAM is powered down, the pass gate is configured in a locked state preventing access to the NVRAM.

10. The system of claim 9 , wherein the pass gate value is fetched from a programmable memory cell.

11. The system of claim 9 , wherein the pass gate value is stored in a NVRAM fuse.

12. The system of claim 9 , wherein the means for unlocking the pass gate comprises one or more switches for electrically coupling a random access memory (RAM) controller residing on the SoC to the non-volatile cell array.

13. The system of claim 9 , wherein the unlock password comprises an encrypted message.

14. The system of claim 13 , wherein the means for comparing the unlock password to the pass gate value provisioned in the NVRAM comprises:
means for decrypting the encrypted message comprising the unlock password.

15. The system of claim 9 , further comprising:
means for maintaining the pass gate in a locked state if the unlock password does not match the pass gate value.

16. The system of claim 9 , further comprising:
means for maintaining a self-destruct counter to keep track of a number of failed password exchanges between the SoC and the NVRAM; and
means for permanently locking the pass gate if the self-destruct counter exceeds a threshold.

17. A non-volatile random access memory device comprising:
a non-volatile cell array;
a fuse within the non-volatile random access memory device comprising a pass gate value; and
a pass gate within the non-volatile random access memory device configured to prevent read/write access to the non-volatile cell array if an unlock password received from a system on chip (SoC) coupled to the non-volatile random access memory device in response to a trusted boot program executing on the SoC does not match the pass gate value,
wherein, when the non-volatile random access memory device is powered down, the pass gate is configured in a locked state preventing access to the non-volatile random access memory device.

18. The non-volatile random access memory device of claim 17 , further comprising logic configured to:
fetch the pass gate value from the fuse;
compare the received unlock password to the pass gate value; and
send a control signal to the pass gate in response to the comparison of the unlock password to the pass gate value.

19. The non-volatile random access memory device of claim 17 , further comprising logic configured to:
maintain a self-destruct counter to keep track of a number of times that the received unlock password does not match the pass gate value; and
if the self-destruct counter exceeds a threshold, permanently lock the pass gate.

20. The non-volatile random access memory device of claim 17 , wherein the pass gate is configured to enable read/write access to the non-volatile cell array if the received unlock password matches the pass gate value.

21. The non-volatile random access memory device of claim 17 , wherein the fuse comprises a programmable memory cell that stores the pass gate value.

22. The non-volatile random access memory device of claim 17 , wherein the pass gate comprises one or more switches electrically coupled to the non-volatile cell array.

23. The non-volatile random access memory device of claim 17 , wherein the unlock password comprises an encrypted message, and further comprising logic configured to decrypt the encrypted message.

24. A system for providing secure access to a non-volatile random access memory, the system comprising:
a system on chip (SoC) comprising a random access memory (RAM) controller; and
a non-volatile random access memory (NVRAM) electrically coupled to the RAM controller, the NVRAM comprising:
a non-volatile cell array;
a NVRAM fuse comprising a pass gate value; and
a pass gate configured to prevent read/write access to the non-volatile cell array if an unlock password received from the RAM controller does not match the pass gate value,

wherein, when the NVRAM is powered down, the pass gate is configured in a locked state preventing access to the NVRAM.

25. The system of claim 24 , wherein the NVRAM further comprises logic configured to:
fetch the pass gate value from the fuse;
compare the received unlock password to the pass gate value; and
send a control signal to the pass gate in response to the comparison of the unlock password to the pass gate value.

26. The system of claim 25 , wherein the NVRAM further comprises logic configured to:
maintain a self-destruct counter to keep track of a number of times that the received unlock password does not match the pass gate value; and
if the self-destruct counter exceeds a threshold, permanently lock the pass gate.

27. The system of claim 26 , wherein the pass gate is configured to enable read/write access to the non-volatile cell array if the received unlock password matches the pass gate value.

28. The system of claim 24 , wherein the fuse comprises a programmab

Assignees

• Qualcomm Inc

Inventors

• Chun Dexter
• Li Yanru

Classifications

• G06F21/79 Primary

  in semiconductor storage media, e.g. directly-addressable memories · CPC title

• G06F2212/1052

  Security improvement · CPC title

• G06F21/602

  Providing cryptographic facilities or services · CPC title

• G06F12/1425 Primary

  the protection being physical, e.g. cell, word, block · CPC title