High current limit trim apparatus and methodology

Patent metadata

Field	Value
Publication number	US-10386876-B2
Application number	US-201615231472-A
Country	US
Kind code	B2
Filing date	Aug 8, 2016
Priority date	Aug 7, 2015
Publication date	Aug 20, 2019
Grant date	Aug 20, 2019

Abstract

A circuit protective system. The system has: (i) an input for sensing an operational voltage responsive to a current flowing through a transistor; (ii) circuitry for applying a forced voltage at the input; (iii) voltage-to-current conversion circuitry for outputting a reference current in response to the forced voltage at the input; (iv) circuitry for providing a reference trim current in response to a trim indicator; and (v) comparison circuitry for outputting a limit signal in response to a comparison of the reference current and the reference trim current.

First claim

The invention claimed is:

1. A system, comprising:
a substrate having a supply voltage input, a substrate resistance, a transistor formed in the substrate, and a regulated voltage output coupled in series, the transistor including a drain coupled to the substrate resistance, a source, and a gate; and
test circuitry including:
an operational voltage input coupled to between the substrate resistance and the drain;
forcing circuitry having an output coupled to the operational voltage input, the forcing circuitry adapted to apply a forced voltage at the operational voltage input;
voltage to current circuitry having an input coupled to the operational voltage input and having a reference current output, the voltage to current circuitry adapted to output a reference current on the reference current output in response to the forced voltage;
trim current circuitry having a trim current output coupled to the reference current output, the trim current circuitry adapted to provide a trim current on the trim current output in response to a received trim indicator; and
comparison circuitry having an input coupled to the reference current output and the trim current output and having a limit output, the comparison circuitry adapted to output a limit signal on the limit output in response to the reference current and the trim current.

2. The system of claim 1 in which the test circuitry includes:
current source circuitry coupled to the regulated voltage output for enabling a predetermined current through a source-to-drain path of the transistor; and
difference circuitry coupled to the supply voltage input and the drain for measuring a voltage difference across the substrate resistance.

3. The system of claim 2 in which the substrate resistance of the substrate equals the voltage difference across the substrate resistance divided by the predetermined current.

4. The system of claim 2 in which the predetermined current is at least one order of magnitude less than an operational current limit through a source-to-drain path of the transistor.

5. The system of claim 2 in which the predetermined current is at least two orders of magnitude less than an operational current limit through a source-to-drain path of the transistor.

6. The system of claim 1 and including trip circuitry coupled to an input of the voltage-to-current circuitry for determining a trip voltage at which the comparison circuitry changes a state of the limit signal.

7. The system of claim 6 in which the trim indicator is set in response to the trip voltage.

8. The system of claim 6 in which the test circuitry includes:
iteration circuitry coupled to the trim current circuity for iteratively applying a plurality of different trim indicators; and
measuring circuitry coupled to the trip circuity for measuring a respective trip voltage corresponding to each trim indicator in the plurality of trim indicators.

9. The system of claim 8 in which the test circuitry includes:
final trim circuitry coupled to the limit output for selecting a final trim indicator in response to a respective ratio of each respective trip voltage divided by the substrate resistance.

10. The system of claim 9 in which the test circuitry includes programming circuitry coupled to the trim current circuitry for programming the final trim indicator to the circuitry for providing a reference trim current.

11. The system of claim 8 in which the measuring circuitry for measuring a respective trip voltage further includes circuitry for sweeping across a voltage range that includes the trip voltage.

12. The system of claim 1 and further including a load driven by the transistor.

13. A circuit protective system, comprising:
an input adapted to be coupled to between a drain of a transistor and a substrate resistance;
a node coupled to the input;
a first transistor having a source/drain path coupled to the node and that senses an operational voltage responsive to a current flowing through the transistor;
a second transistor having a source/drain path couple to the node and that selectively applies a forced voltage to the node;
voltage-to-current conversion circuitry including an amplifier with an input coupled to the node and an amplifier output, the amplifier outputs a reference current on the amplifer output in response to the forced voltage at the node;
trim circuitry that provides a reference trim current on a trim output in response to receiving a trim indicator; and
comparison circuitry having inputs coupled to the trim output and to the amplifier output and that outputs a limit signal on a limit output in response to a comparison of the reference current and the reference trim current.

14. The system of claim 13 in which the trim circuitry includes a digital to analog converter that receives the trim indicator as an input and that outputs the reference trim current.

15. The system of claim 13 including test circuitry coupled to the input for determining a substrate resistance of the substrate.

16. A method of determining a current trim indicator for a circuit protective system that includes a transistor with a substrate resistance and a circuit responsive to a trip voltage, the method comprising:
determining the substrate resistance;
iteratively applying a plurality of different trim indicators to the circuit protective system;
determining a respective trip voltage corresponding to each trim indicator in the plurality of trim indicators; and
selecting a final trim indicator from the plurality of trim indicators, in which the final trim indicator corresponds to a predetermined current limit represented by a ratio of a trip voltage divided by the substrate resistance.

17. The method of claim 16 in which:
the step of determining the substrate resistance includes enabling a predetermined current through a source-to-drain path of the transistor; and
in which the predetermined current is at least one order of magnitude less than an operational current limit through a source-to-drain path of the transistor.

18. The method of claim 16 in which:
the step of determining the substrate resistance includes enabling a predetermined current through a source-to-drain path of the transistor; and
in which the predetermined current is at least two orders of magnitude less than an operational current limit through a source-to-drain path of the transistor.

Assignees

• Texas Instruments Inc

Inventors

• Rahman Md Abidur
• Aras Sualp
• Nguyen Tri Cao

Classifications

• G05F1/571 Primary

  with overvoltage detector · CPC title

• G05F1/569

  for protection · CPC title

• H02H3/006

  Calibration or setting of parameters · CPC title

• G05F1/573

  with overcurrent detector · CPC title

• H02H3/087

  for DC applications · CPC title