Hybrid memory module and system and method of operating the same

Patent metadata

Field	Value
Publication number	US-10380022-B2
Application number	US-201414536588-A
Country	US
Kind code	B2
Filing date	Nov 7, 2014
Priority date	Jul 28, 2011
Publication date	Aug 13, 2019
Grant date	Aug 13, 2019

Abstract

A memory module comprises a volatile memory subsystem configured to coupled to a memory channel in computer system and capable of serving as main memory for the computer system, a non-volatile memory subsystem providing storage for the computer system, and a module controller coupled to the volatile memory subsystem, the non-volatile memory subsystem, and the C/A bus. The module controller is configured to control intra-module data transfers between the volatile memory subsystem and the non-volatile memory subsystem. The module controller is further configured to monitor C/A signals on the C/A bus and schedule the intra-module data transfers in accordance with the C/A signals so that the intra-module data transfers do not conflict with accesses to the volatile memory subsystem by the memory controller.

First claim

We claim:

1. A memory module for use in a computer system, the computer system including a memory controller coupled to the memory module via a system bus, the system bus including a data bus and a control/address (C/A) bus, comprising:
a volatile memory subsystem coupled to the system bus and capable of serving as main memory for the computer system, the volatile memory subsystem including dynamic random access memory (DRAM) devices;
a non-volatile memory subsystem configured to provide data storage for the computer system; and
a module controller coupled to the volatile memory subsystem, the non-volatile memory subsystem, and the system bus, wherein the module controller is configured to read first data from the non-volatile memory subsystem in response to a first command received via the system bus, the first command being a command to transfer data from the non-volatile memory subsystem to the volatile memory subsystem, wherein the module controller is further configured to provide at least one portion of the first data to the volatile memory subsystem a certain time period after receiving a dummy write memory command via the C/A bus so that the at least one portion of the first data appear at inputs/outputs (I/O) of the DRAM devices in accordance with a latency parameter of the DRAM devices, wherein the volatile memory subsystem is configured to receive the at least a portion of the first data in response to the dummy write memory command.

2. The memory module of claim 1 , further comprising a dedicated data path for data transfers between the volatile memory subsystem and the non-volatile memory subsystem, wherein the dedicated data path includes first data signal lines between the volatile memory subsystem and the module controller, and second data signal lines between the module controller and the non-volatile memory subsystem, wherein the dedicated data path does not include the data bus, wherein the first data is transferred from the non-volatile memory subsystems to the module controller via the second data signal lines, and wherein the at least one portion of the first data is transferred from the module controller to the volatile memory subsystem via the first data signal lines.

3. The memory module of claim 2 , further comprising a data buffer coupled to the module controller, wherein the dedicated data path also includes third data signal lines between the data buffer and the module controller, and wherein the at least one portion of the first data is stored in the data buffer before being provided to the volatile memory subsystem.

4. The memory module of claim 3 , wherein the data buffer is coupled to the module controller via the third data signal lines and a set of module C/A signal lines, and wherein the module controller issues a memory command to the data buffer via the set of module C/A signal lines to cause the data buffer to output the at least one portion of the first data before providing the at least one portion of the first data to the volatile memory subsystem.

5. The memory module of claim 4 , wherein the module controller is configured to monitor memory commands on the C/A bus and to delay issuing further memory commands to the data buffer to cause the data buffer to out one or more portions of the first data in response to one or more memory commands received via the C/A bus, the one or more memory commands are one or more normal memory access commands directed to the volatile memory subsystem.

6. The memory module of claim 1 , wherein the module controller includes at least one processor, and wherein the module controller is configured to pre-process the first data read from the non-volatile memory subsystem before providing the at least one portion of the first data to the volatile memory subsystem.

7. The memory module of claim 6 , wherein the module controller is configured to search the first data read from the non-volatile memory subsystem in accordance with a set of criteria, and where the at least one portion of the first data comprises a portion of the first data from the non-volatile memory subsystem meeting the set of criteria.

8. The memory module of claim 2 , wherein the non-volatile memory subsystem includes a plurality of non-volatile memory packages including a first set of non-volatile memory packages for storing data and at least one non-volatile memory package for storing parity bits associated with the data, and wherein the dedicated data path further includes an error correction circuit that restores corrupted data from the non-volatile memory system using the parity bits.

9. The memory module of claim 1 , wherein the module controller is further configured to snoop second data output from the volatile memory subsystem in response to a second command received via the C/A bus and a dummy read memory command received via the C/A bus, wherein the volatile memory subsystem is configured to output the second data in response to the dummy read memory command, and wherein the module controller is further configured to transfer the second data to the non-volatile memory subsystem in accordance with the second command and a set of data signals received via the data bus, the second command being a command to transfer data from the volatile memory subsystem to the non-volatile memory subsystem, the set of data signals being associated with the second command.

10. The memory module of claim 9 , further comprising a data buffer, wherein the data buffer comprises DRAM and wherein the memory module is configured to store the second data into the data buffer after snooping the second data output from the volatile memory subsystem and before transferring the second data into the non-volatile memory subsystem.

11. The memory module of claim 9 , wherein the module controller is configured to store the second data into the non-volatile memory subsystem in DRAM format.

12. The memory module of claim 1 , further comprising a network interface circuit, wherein the memory module is configured to couple directly to another memory module via the network interface circuit and to receive data from and transmit data to the other memory module via the network interface circuit.

13. The memory module of claim 1 , further comprising a network interface circuit, wherein the memory module is configured to couple directly to a computer network via the network interface circuit and to receive data from and transmit data to the computer network via the network interface circuit.

14. A method performed by a memory module coupled to a memory controller via a system bus in a computer system, the system bus including a data bus and a control/address (C/A) bus, the memory module including a volatile memory subsystem, a non-volatile memory subsystem, the method comprising:
receiving a first command from the memory controller via the C/A bus;
in response to the first command being a command to transfer first data from the non-volatile memory subsystem to the volatile memory subsystem, receiving via the data bus first information associated with the first command, the first information including at least one of a first address in the non-volatile memory subsystem at which the first data is located and a second address in the volatile memory subsystem to which the first data is to be transferred, and reading the first data requested by the first command from the non-volatile memory subsystem;
receiving a dummy write memory command from the memory controller via the C/A bus; and
in response to the dummy write memory command being associated with the first command, providing at least one portion of the first data to the volatile memory subsystem a c

Assignees

• Netlist Inc

Inventors

• Lee Hyun
• Bhakta Jayesh R
• Chen Chi She
• Solomon Jeffery C
• Martinez Mario Jesus
• Le Hao
• Choi Soon J

Classifications

• G06F2212/214

  Solid state disk · CPC title

• G06F2212/313

  In storage device · CPC title

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title

• G06F13/28

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F3/0656

  Data buffering arrangements · CPC title