Metal dot substrate and method of manufacturing metal dot substrate
US-2015293025-A1 · Oct 15, 2015 · US
US10378103B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10378103-B2 |
| Application number | US-201816152190-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 4, 2018 |
| Priority date | Jul 26, 2016 |
| Publication date | Aug 13, 2019 |
| Grant date | Aug 13, 2019 |
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A molecular sensor includes a substrate defining a substrate plane, and a plurality of pairs of electrode sheets above or below the substrate at an angle to the substrate plane. The molecular sensor further includes a plurality of inner dielectric sheets between each electrode sheet in each pair of electrode sheets of the plurality of pairs, and an outer dielectric sheet between each pair of electrode sheets of the plurality of pairs.
Opening claim text (preview).
What is claimed is: 1. A method of manufacturing structure usable in a molecular sensor device, the method comprising: forming a stack by at least: providing a first outer dielectric layer; depositing a first electrode layer on the first outer dielectric layer; depositing an inner dielectric layer on the first electrode layer; depositing a second electrode layer on the inner dielectric layer; and depositing a second outer dielectric layer on the second electrode layer, wherein the inner dielectric layer has a first thickness and the second outer dielectric layer has a second thickness at least one order of magnitude greater than the first thickness, wherein the first electrode layer and second electrode layer are deposited with a thickness of 1 to 40 nm, wherein the inner dielectric layer is deposited with a thickness of 1 to 40 nm, and wherein the second outer dielectric layer is deposited with a thickness between 50 to 2,000 nm; slicing through the stack at least once at an angle to the layers in the stack to form a plurality of chips from the sliced portions of the stack; and attaching the plurality of chips to a substrate so that the sliced portions of the first electrode layer and the second electrode layer form a plurality of pairs of electrode sheets at an angle to a substrate plane defined by the substrate, and so that the sliced portions of the inner dielectric layer forms a plurality of inner dielectric sheets with each inner dielectric sheet between each electrode sheet in each pair of electrode sheets. 2. The method of claim 1 , wherein forming the stack further includes repeating the deposition of the first electrode layer, the inner dielectric layer, the second electrode layer, and the second outer dielectric layer at least once so that each chip of the plurality of chips includes multiple pairs of electrode sheets. 3. The method of claim 1 , further comprising forming a groove located on an exposed end portion of each inner dielectric sheet. 4. The method of claim 1 , further comprising depositing a dielectric cover layer at an angle or perpendicular to the plurality of pairs of electrode sheets opposite the substrate to define a gap exposing a portion of the plurality of pairs of electrode sheets. 5. The method of claim 1 , further comprising roughening an exposed edge of each electrode sheet. 6. The method of claim 1 , further comprising depositing a gate electrode parallel to the substrate plane and perpendicular to an electrode plane defined by an electrode sheet in the plurality of pairs of electrode sheets. 7. The method of claim 1 , further comprising forming a plurality of channels, each channel arranged to introduce a fluid to exposed portions of at least two pairs of electrode sheets of the plurality of pairs of electrode sheets.
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