Method of fabricating a flexible substrate and the flexible substrate fabricated thereby

Patent metadata

Field	Value
Publication number	US-10374093-B2
Application number	US-201715812231-A
Country	US
Kind code	B2
Filing date	Nov 14, 2017
Priority date	Dec 8, 2016
Publication date	Aug 6, 2019
Grant date	Aug 6, 2019

Abstract

Embodiments of the inventive concepts provide a method of fabricating a flexible substrate and the flexible substrate fabricated thereby. The method includes printing a gate catalyst pattern on a separation layer, forming a gate plating pattern on the gate catalyst pattern, forming a gate insulating layer on the gate plating pattern, printing a source catalyst pattern and a drain catalyst pattern spaced apart from each other on the gate insulating layer, and forming a source plating pattern and a drain plating pattern on the source catalyst pattern and the drain catalyst pattern, respectively.

First claim

What is claimed is:

1. A method of fabricating a flexible substrate, the method comprising:
forming a separation layer on a carrier substrate;
printing a gate catalyst pattern on the separation layer;
forming a gate plating pattern on the gate catalyst pattern;
forming a gate insulating layer on the gate plating pattern;
printing a source catalyst pattern and a drain catalyst pattern spaced apart from each other on the gate insulating layer;
forming a source plating pattern and a drain plating pattern on the source catalyst pattern and the drain catalyst pattern, respectively, such that the source plating pattern and the drain plating pattern are spaced apart from each other, exposing the gate insulating layer between the source plating pattern and the drain plating pattern;
forming an active pattern covering the source plating pattern, the drain plating pattern, and the gate insulating layer exposed between the source plating pattern and the drain plating pattern;
forming a first substrate layer that is flexible and covers an entire top surface of the carrier substrate on which the active pattern is formed; and
removing the separation layer and the carrier substrate.

2. The method of claim 1 , wherein the forming of the gate insulating layer comprises:
printing and thermally treating a precursor solution including a material of the gate insulating layer.

3. The method of claim 1 , further comprising:
forming a second substrate layer, which is flexible, on the separation layer before the printing of the gate catalyst pattern.

4. The method of claim 1 , further comprising:
forming a back-channel protecting layer covering the active pattern before the forming of the first substrate layer.

5. The method of claim 1 , further comprising:
forming a gas barrier layer covering an entire top surface of the carrier substrate having the active pattern before the forming of the first substrate layer.

6. The method of claim 1 , further comprising:
forming a protective film covering at least a portion of the first substrate layer after the removing of the separation layer and the carrier substrate.

7. The method of claim 1 , wherein the separation layer and the gate plating pattern are formed of different materials from each other.

Assignees

• Electronics & Telecommunications Res Inst

Inventors

• Cho Doo-Hee
• Park Young Sam
• Byun Chunwon
• Yu Byoung Gon
• Lee Jonghee
• Lee Hyunkoo
• Cho Nam Sung

Classifications

• H10P72/7426

  used as a support during build up manufacturing of active devices · CPC title

• H10P72/7412

  the auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support · CPC title

• H10P14/3434

  being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title

• H10P14/3426

  Oxides · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title