3D transistor having a gate stack including a ferroelectric film

Patent metadata

Field	Value
Publication number	US-10374086-B2
Application number	US-201615369809-A
Country	US
Kind code	B2
Filing date	Dec 5, 2016
Priority date	Dec 4, 2015
Publication date	Aug 6, 2019
Grant date	Aug 6, 2019

Abstract

A three-dimensional (3D) transistor includes a ferroelectric film between the gate and the channel. The 3D transistor can be characterized as a 3D Negative Capacitance (NC) transistor due to the negative capacitance resulting from the ferroelectric film. Performance of the transistor is optimized by manipulating the structure and/or by the selection of materials. In one example, the capacitance of the ferroelectric film (CFE) is matched to the sum of the gate capacitance (CMOS) and the gate edge capacitance (CEDGE), wherein the gate edge capacitance (CEDGE) is the capacitance at the edge of the gate and between the gate and the source and its extension, and the gate and the drain and its extension.

First claim

What is claimed is:

1. A 3D transistor comprising:
a drain;
a source;
a channel longitudinally extending between the drain and the source;
a gate positioned over at least two lateral sides of the channel and having a gate length less than 22 nm; and
a ferroelectric film between the gate and the channel for at least a portion of the region between the gate and the channel, the 3D transistor having a structure configured to operate with less than 59 mV per decade subthreshold swing at room temperature, the ferroelectric film having a ferroelectric capacitance substantially matched, over an operating range of a gate voltage, to a sum of a gate to channel capacitance (C MOS ) and a gate edge capacitance (C EDGE ), the C EDGE resulting between at the edge portion of the gate and between the gate and the source and the source extension, and the gate and the drain and the drain extension.

2. The 3D transistor of claim 1 , wherein the 3D transistor has a structure selected from the group comprising FinFET, nanowire FET, Gate-All-Around FET, nanowire FinFET, Omega FET, and nanotube FET structures and combinations thereof.

3. The 3D transistor of claim 1 , wherein a ferroelectric capacitance of the ferroelectric film is substantially matched to a gate to channel capacitance (C MOS ) over an operating range of a gate voltage.

4. The 3D transistor of claim 1 , wherein the ferroelectric film has a thickness less than 10.0 nm.

5. The 3D transistor of claim 4 , wherein the ferroelectric film has a thickness less than 7.0 nm.

6. The 3D transistor of claim 1 , wherein the ferroelectric film comprises a film selected from the group comprising: hafnium zirconium oxide, hafnium oxide, zirconium oxide, Pb(Zr,Ti)O, and BaTiO.

7. The 3D transistor of claim 1 , further comprising an internal conductive gate positioned between the channel and the ferroelectric film.

8. The 3D transistor of claim 7 , wherein a material of the internal gate is selected from the group comprising TiN, TaN, Ru, W, and Si.

9. The 3D transistor of claim 7 , wherein the gate is in close proximity to only a portion of the internal gate and configured to reduce the effective area of the gate to internal gate ferroelectric capacitor area.

10. The 3D transistor of claim 1 , further comprising a dielectric film between the channel and the ferroelectric film.

11. The 3D transistor of claim 10 , wherein the dielectric film is selected from the group consisting of SiO2 and SiON and wherein the gate is a metal gate.

12. The 3D transistor of claim 10 , further comprising a gate dielectric with an effective oxide thickness (EOT) more than 0.8 nm.

13. The 3D transistor of claim 1 , wherein the structure is configured to have a current-voltage characteristic similar to a MOSFET without a ferroelectric film, the current-voltage characteristic not having significant hysteresis.

14. A method of fabricating a three-dimensional transistor configured to operate with less than 59 mV per decade subthreshold swing at room temperature, the method comprising:
forming a drain;
forming a source;
forming a channel longitudinally extending between the drain and the source;
forming a gate positioned over at least two lateral sides of the channel and having a gate length less than 22 nm; and
forming a ferroelectric film between the gate and the channel for at least a portion of the region between the gate and the channel; and
substantially matching, over an operating range of a gate voltage, a ferroelectric capacitance of the ferroelectric film to a sum of a gate to channel capacitance (C MOS ) and a gate edge capacitance (C EDGE ), the C EDGE resulting at the edge of the gate and between the gate and the source and its extension, and the gate and the drain and its extension.

15. The method of claim 14 , wherein the forming the ferroelectric film comprises forming the ferroelectric film to have an effective oxide thickness (EOT) greater than 0.8 nm.

16. The method of claim 14 , further comprising forming a gate dielectric between the channel and the ferroelectric film, wherein the gate dielectric and the ferroelectric film are formed in the same deposition tool without breaking vacuum.

17. A 3D transistor comprising:
a drain;
a source;
a channel longitudinally extending between the drain and the source;
a gate positioned over at least two lateral sides of the channel and having a gate length less than 22 nm; and
a ferroelectric film between the gate and the channel for at least a portion of the region between the gate and the channel, the 3D transistor having a structure configured to operate with less than 59 mV per decade subthreshold swing at room temperature, the ferroelectric film having a ferroelectric capacitance substantially matched to a gate to channel capacitance (C MOS ) over an operating range of a gate voltage.

18. The 3D transistor of claim 17 , wherein the 3D transistor has a structure selected from the group comprising FinFET, nanowire FET, Gate-All-Around FET, nanowire FinFET, Omega FET, and nanotube FET structures and combinations thereof.

19. The 3D transistor of claim 17 , wherein a ferroelectric capacitance of the ferroelectric film is substantially matched, over an operating range of a gate voltage, to a sum of a gate to channel capacitance (C MOS ) and a gate edge capacitance (C EDGE ), the C EDGE resulting between at the edge portion of the gate and between the gate and the source and the source extension, and the gate and the drain and the drain extension.

20. The 3D transistor of claim 17 , wherein the ferroelectric film has a thickness less than 10.0 nm.

21. The 3D transistor of claim 20 , wherein the ferroelectric film has a thickness less than 7.0 nm.

22. The 3D transistor of claim 17 , wherein the ferroelectric film comprises a film selected from the group comprising: hafnium zirconium oxide, hafnium oxide, zirconium oxide, Pb(Zr,Ti)O, and BaTiO.

23. The 3D transistor of claim 17 , further comprising an internal conductive gate positioned between the channel and the ferroelectric film.

24. The 3D transistor of claim 17 , further comprising a dielectric film between the channel and the ferroelectric film.

25. The 3D transistor of claim 24 , wherein the dielectric film is selected from the group consisting of SiO2 and SiON and wherein the gate is a metal gate.

26. The 3D transistor of claim 24 , further comprising a gate dielectric with an effective oxide thickness (EOT) more than 0.8 nm.

27. A 3D transistor comprising:
a drain;
a source;
a channel longitudinally extending between the drain and the source;
a gate positioned over at least two lateral sides of the channel and having a gate length less than 22 nm;
a ferroelectric film between the gate and the channel for at least a portion of the region between the gate and the channel;
an internal conductive gate positioned between the channel and the ferroelectric film, the gate in close proximity to only a portion of the internal gate and configured to reduce the effective area of the gate to internal gate ferroelectric capacitor area, the 3D transistor having a structure configured to operate with less than 59 mV per decade subthreshold swing at room temperature.

28. The 3D transistor of claim 27 , wherein the 3D transistor has a structure selected from the group comprising FinFET, nanowire FET, Gate-All-Around FET, nanowire FinFE

Assignees

• Univ California

Inventors

• Hu Chenming

Classifications

• H01L29/516

  Electricity · mapped topic

• H01L29/78696

  Electricity · mapped topic

• H01L29/775

  Electricity · mapped topic

• H01L29/778

  Electricity · mapped topic

• H01L29/78391 Primary

  Electricity · mapped topic