Tunnel field effect transistors

US10374068B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10374068-B2
Application numberUS-201715403998-A
CountryUS
Kind codeB2
Filing dateJan 11, 2017
Priority dateDec 17, 2009
Publication dateAug 6, 2019
Grant dateAug 6, 2019

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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Abstract

Official abstract text for this publication.

Tunnel field effect devices and methods of fabricating tunnel field effect devices are described. In one embodiment, the semiconductor device includes a first drain region of a first conductivity type disposed in a first region of a substrate, a first source region of a second conductivity type disposed in the substrate, the second conductivity type being opposite the first conductivity type, a first channel region electrically coupled between the first source region and the first drain region, the first source region underlying a least a portion of the first channel region, and a first gate stack overlying the first channel region.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor device comprising: a first drain region of a first conductivity type disposed in a first region of a substrate; a first source region of a second conductivity type disposed in said substrate, said second conductivity type being opposite said first conductivity type; a first channel region of the first conductivity type electrically coupled between said first source region and said first drain region; a first gate stack overlying said first channel region; a first doped region of the first conductivity type disposed between the first source region and the first drain region, wherein the first doped region is doped to a lower doping than the first source region, and wherein at least a portion of the first doped region is in direct contact with a bottom surface of the first channel region; and a second doped region of the second conductivity type disposed between the first source region and the first drain region, wherein the second doped region is doped to a higher doping than the first doped region, wherein at least a portion of the second doped region is in direct contact with the bottom surface of the first channel region, and wherein a tunnel junction is formed at the intersection between the first source region and the first channel region, wherein the first channel region has a lower dopant concentration than a dopant concentration of the first source region so that, at the tunnel junction between the first source region and the first channel region, a net doping concentration varies abruptly from the first source region to the first channel region. 2. The device of claim 1 , wherein the first channel region comprises germanium, wherein the germanium content is at least 15% by concentration. 3. The device of claim 1 , wherein the second doped region comprises a crystal orientation that enhances a tunnel current between the first channel region and the second doped region, wherein the crystal orientation of the second doped region is different than a crystal orientation within the substrate, wherein the substrate comprises a bulk substrate. 4. The device of claim 1 , further comprising: a second drain region of the second conductivity type disposed in a second region of the substrate; a second source region of the first conductivity type disposed in said substrate; a second channel region electrically coupled between said second source region and said second drain region; and a second gate stack overlying said second channel region. 5. The device of claim 1 , wherein the net doping concentration is less than the lower dopant concentration.

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Classifications

  • of a molecular ion, e.g. decaborane · CPC title

  • characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

  • of electrically inactive species · CPC title

  • into Group IV semiconductors · CPC title

  • Electricity · mapped topic

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What does patent US10374068B2 cover?
Tunnel field effect devices and methods of fabricating tunnel field effect devices are described. In one embodiment, the semiconductor device includes a first drain region of a first conductivity type disposed in a first region of a substrate, a first source region of a second conductivity type disposed in the substrate, the second conductivity type being opposite the first conductivity type, a…
Who is the assignee on this patent?
Infineon Technologies Ag, Indian Inst Technology Bombay
What technology area does this patent fall under?
Primary CPC classification H01L29/66977. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 06 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).