Methods and apparatus for three-dimensional nonvolatile memory

Patent metadata

Field	Value
Publication number	US-10374013-B2
Application number	US-201715473671-A
Country	US
Kind code	B2
Filing date	Mar 30, 2017
Priority date	Mar 30, 2017
Publication date	Aug 6, 2019
Grant date	Aug 6, 2019

Abstract

A method is provided that includes forming a bit line above a substrate; forming a word line above the substrate, and forming a non-volatile memory cell between the bit line and the word line. The non-volatile memory cell includes a non-volatile memory material coupled in series with an isolation element. The isolation element includes a first electrode, a second electrode, and a semiconductor layer and a barrier layer disposed between the first electrode and the second electrode.

First claim

The invention claimed is:

1. A method comprising:
forming a bit line above a substrate;
forming a word line above the substrate;
etching the word line to form a void adjacent an end of the word line;
forming a non-volatile memory material in the void; and
forming a non-volatile memory cell between the bit line and the word line, the non-volatile memory cell comprising the non-volatile memory material coupled in series with an isolation element,
wherein:
the isolation element comprises a first electrode, a second electrode, and a semiconductor layer and a barrier layer disposed between the first electrode and the second electrode.

2. The method of claim 1 , wherein the isolation element further comprises a first capping layer disposed between the semiconductor layer and the barrier layer.

3. The method of claim 1 , wherein the isolation element further comprises a second capping layer disposed between the semiconductor layer and the second electrode.

4. The method of claim 1 , wherein the first electrode comprises one or more of copper, silver, and nickel.

5. The method of claim 1 , wherein the second electrode comprises one or more of titanium nitride, a conductive carbon, platinum, ruthenium, palladium, iridium, titanium aluminum nitride, and tungsten.

6. The method of claim 1 , wherein the semiconductor layer comprises one or more of silicon, germanium, silicon-germanium, hafnium oxide, silicon oxide, titanium oxide, tungsten oxide and zinc oxide.

7. The method of claim 1 , wherein the barrier layer comprises one or more of titanium, tantalum, titanium nitride, tantalum nitride, tungsten nitride, and tantalum carbide.

8. The method of claim 1 , wherein the bit line comprises the first electrode or the second electrode.

9. The method of claim 1 , wherein the non-volatile memory material comprises a reversible resistance-switching memory element.

10. The method of claim 1 , wherein the non-volatile memory material comprises one or more of a phase change material, a ferroelectric material, a metal oxide, and a barrier modulated switching structure.

11. A method comprising:
forming a bit line disposed in a first direction above a substrate;
forming a word line disposed in a second direction above the substrate, the second direction perpendicular to the first direction;
etching the word line to form a void at an end of the word line; and
forming a non-volatile memory cell at an intersection of the bit line and the word line by:
forming a non-volatile memory material in the void; and
forming an isolation element adjacent the non-volatile memory material, the isolation element comprising a first electrode, a second electrode, and a semiconductor layer and a barrier layer disposed between the first electrode and the second electrode.

12. The method of claim 11 , wherein the isolation element further comprises a first capping layer disposed between the semiconductor layer and the barrier layer.

13. The method of claim 11 , wherein the isolation element further comprises a second capping layer disposed between the semiconductor layer and the second electrode.

14. The method of claim 11 , wherein the first electrode comprises one or more of copper, silver, and nickel.

15. The method of claim 1 , wherein the semiconductor layer comprises one or more of silicon, germanium, silicon-germanium, hafnium oxide, silicon oxide, titanium oxide, tungsten oxide and zinc oxide.

16. The method of claim 11 , wherein the barrier layer comprises one or more of titanium, tantalum, titanium nitride, tantalum nitride, tungsten nitride, and tantalum carbide.

17. The method of claim 1 , wherein the non-volatile memory material comprises a reversible resistance-switching memory element.

18. The method of claim 1 , wherein the non-volatile memory material comprises one or more of a phase change material, a ferroelectric material, a metal oxide, and a barrier modulated switching structure.

Assignees

• Sandisk Technologies Llc

Inventors

• Bandyopadhyay Abhijit
• Petti Christopher J
• Nguyen Natalie
• Le Brian

Classifications

• H10W20/0698

  Local interconnections · CPC title

• H01L27/249 Primary

  Electricity · mapped topic

• H01L45/1226

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic

• H01L43/08

  Electricity · mapped topic