Stack type semiconductor memory device

Patent metadata

Field	Value
Publication number	US-2016155779-A1
Application number	US-201615006782-A
Country	US
Kind code	A1
Filing date	Jan 26, 2016
Priority date	Dec 15, 2011
Publication date	Jun 2, 2016
Grant date	—

Abstract

A stack type memory device and a method of manufacturing the same are provided. The stack type memory device includes a semiconductor substrate, a plurality of active layers stacked on the semiconductor substrate, and a gate structure overlapping the plurality of active layers. The gate structure includes a side gate region overlapping sides of the plurality of active layers and a top gate region overlapping a top of an uppermost active layer.

First claim

What is claimed is:

1 . A stack type memory device, comprising
a semiconductor substrate; a plurality of active layers stacked on the semiconductor substrate; and a gate structure overlapping the plurality of active layers, wherein the gate structure includes a side gate region overlapping sides of the plurality of active layers and a top gate region overlapping a top of an uppermost active layer.

2 . The stack type memory device of claim 1 , wherein the plurality of active layers are formed in a stripe pattern, and
the gate structure extends to a direction substantially perpendicular to an extending direction of the stripe pattern.

3 . The stack type memory device of claim 1 , further comprising an interlayer insulating layer which is interposed between the plurality of active layers and insulates the plurality of active layers from each other.

4 . The stack type memory device of claim 1 , wherein drains are formed in the plurality of active layers located in one side of the gate structure and sources are formed in the plurality of active layers located in the other side of the gate structure.

5 . The stack type memory device of claim 4 , further comprising bit lines formed in outer sides of the drains.

6 . The stack type memory device of claim 4 , further comprising variable resistive layers formed in outer sides of the sources.

7 . The stack type memory device of claim 6 , further comprising a common source line which the variable resistive layers are commonly coupled thereto.

8 . The stack type memory device of claim wherein the gate structure has an inverse U-shape.

9 . The stack type memory device of claim 1 , wherein the gate structure includes:
a gate conductive layer; and a gate insulating layer interposed between the gate conductive, layer and the plurality of active layers.

10 . A method of manufacturing a stack type memory device, the method comprising:
alternately stacking an insulating layer and a semiconductor layer on a semiconductor substrate several times; defining a stacked active structure by patterning the insulating layer and the semiconductor layer; forming a first hole through a removing process which pulls back one-end portion of the semiconductor layer of the stacked active structure; forming a bit line in the first hole; forming a second hole through a removing process which pulls back the other-end portion of the semiconductor layer of the stacked active structure; forming a variable resistive layer in the second hole; forming a gate insulating layer on a surface of the stacked active structure; forming a gate conductive layer on a surface of the gate insulating layer; forming a gate structure by patterning the gate conductive layer and the gate insulating layer; and forming a source and a drain by implanting impurities into exposed portions of the semiconductor layer at both sides of the gate structure.

Assignees

• Sk Hynix Inc

Inventors

• Park Nam Kyun

Classifications

• G11C13/003

  Cell access · CPC title

• G11C2213/71

  Three dimensional array · CPC title

• G11C13/0002

  using resistive RAM [RRAM] elements · CPC title

• G11C11/16

  using elements in which the storage effect is based on magnetic spin effect · CPC title

• G11C2213/79

  Array wherein the access device being a transistor · CPC title