Apparatuses and methods for single level cell caching

Patent metadata

Field	Value
Publication number	US-10372369-B2
Application number	US-201816101951-A
Country	US
Kind code	B2
Filing date	Aug 13, 2018
Priority date	Oct 27, 2016
Publication date	Aug 6, 2019
Grant date	Aug 6, 2019

Abstract

Methods and apparatuses for single level cell caching are described. According to one example, a method includes receiving, at a memory device, a first set of data to be stored in a lower page of multilevel memory cells, storing the first set of data in a page of single level memory cells, storing the first set of data in the lower page of the multilevel memory cells, receiving, at the memory device, a second set of data to be stored in an upper page of the multilevel memory cells, and storing the second set of data directly in the upper page of the multilevel memory cells.

First claim

What is claimed is:

1. A method comprising:
receiving, at a control circuit, a first set of write data;
determining whether the first set of write data is to be stored in a lower page or an upper page of a block of multilevel memory cells;
responsive to determining that the first set of write data is to be stored in the lower page, storing the first set of write data in a page of a block of single level memory cells and the lower page of the block of multilevel memory cells; and
responsive to determining that the first set of write data is to be stored in the upper page, storing the first set of write data directly in the upper page of the block of multilevel memory cells without storing the first set of write data in the page of the block of single level memory cells.

2. The method of claim 1 , further comprising:
storing a plurality of sets of write data to lower pages of the block of multilevel memory cells prior to storing the first set of write data in the upper page of the block of multilevel memory cells.

3. The method of claim 1 , further comprising:
receiving, at the control circuit, a second set of write data; and
responsive to storing the first set of write data in the lower page of the block of multilevel memory cells, storing the second set of write data in the upper page of the block of multilevel memory cells.

4. The method of claim 1 , wherein the multilevel memory cells comprise memory cells configured to store at least three bits.

5. The method of claim 1 , further comprising:
responsive to storing the first set of write data in the upper page of the block of memory cells, erasing the block of single level memory cells.

6. The method of claim 1 , further comprising:
providing a confirmation message responsive to storing the first set of write data in the page of the block of single level memory cells.

7. The method of claim 1 , further comprising:
updating a page map responsive to storing the first set of write data in one of the lower page and the upper page of the block of multilevel memory cells.

8. The method of claim 3 , further comprising detecting a power loss event prior to completing storing the second set of write data in the upper page of the block of multilevel memory cells.

9. The method of claim 8 , further comprising copying the first set of write data from the page of the block of single level memory cells to the lower page of the block of multilevel memory cells.

10. The method of claim 9 , reinitiating storing the second set of write data in the upper page of the block of multilevel memory cells.

11. The method of claim 10 , further comprising erasing the page of the block of single level memory cells responsive to completing the storing of the second set of write data in the upper page of the block of multilevel memory cells.

12. The method of claim 9 , further comprising transmitting a confirmation message responsive to storing the first set of write data in the page of the block of single level memory cells.

13. The method of claim 9 , further comprising responsive to detecting the power loss event, determining whether the first set of write data stored in the lower page of the block of multilevel memory cells is corrupted.

14. The method of claim 9 , wherein the first set of write data are stored in the lower page of the block of multilevel memory cells and the second set of write data is stored in the upper page of the block of multilevel memory cells based on a page map.

Assignees

• Micron Technology Inc

Inventors

• Doyle Daniel

Classifications

• G11C11/5635

  Erasing circuits · CPC title

• G11C2211/562

  Multilevel memory programming aspects · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/0644 Primary

  Management of space entities, e.g. partitions, extents, pools · CPC title

• G11C16/16

  for erasing blocks, e.g. arrays, words, groups · CPC title