Array substrate, method of manufacturing the same, and display device

Patent metadata

Field	Value
Publication number	US-10371997-B2
Application number	US-201715726995-A
Country	US
Kind code	B2
Filing date	Oct 6, 2017
Priority date	Apr 30, 2014
Publication date	Aug 6, 2019
Grant date	Aug 6, 2019

Abstract

The present disclosure relates to an array substrate, a method of manufacturing the same and a display device. The array substrate comprises a gate line PAD region and a data line PAD region. In the gate line PAD region of the array substrate, gate-line wirings, which are parallel to the gate lines and are electrically insulated from the gate lines, are provided between adjacent gate lines. In the data line PAD region of the array substrate, data-line wirings, which are parallel to the data lines and are electrically insulated from the data lines, are provided between adjacent data lines. Both of the gate-line wirings and the data-line wirings are conductive wiring segments. By forming the gate-line wirings and the data-line wirings in the PAD region, the ability of resisting scratch of the product can be improved while not deteriorating performance of display of the product.

First claim

What is claimed is:

1. An array substrate, comprising:
a gate line PAD region and a data line PAD region;
wherein the gate line PAD region of the array substrate further comprises:
gate-line wirings, which are parallel to gate lines and are electrically insulated from the gate lines, are formed between adjacent gate lines, and
wherein the data line PAD region of the array substrate further comprises:
data-line wirings, which are parallel to the data lines and are electrically insulated from the data lines, are formed between adjacent data lines,
wherein both the gate-line wirings and the data-line wirings are conductive wiring segments;
wherein the gate-line wirings are configured to be used as restoring gate lines once the gate lines are scratched, and the data-line wirings are configured to be used as restoring data lines once the data lines are scratched;
wherein the gate-line wirings further include first gate-line wiring segments and second gate-line wiring segments being formed between adjacent gate lines, wherein, the first gate-line wiring segments are formed in a same layer as the gate lines are formed, the second gate-line wiring segments are formed above an insulating layer provided on the gate lines; and the first gate-line wiring segments are formed directly under the second gate-line wiring segments and are covered by the insulating layer; and
wherein the data-line wirings further include first data-line wiring segments and second data-line wiring segments being formed between adjacent data lines, wherein, the first data-tine wiring segments are formed in a same layer as the data lines are formed, the second data-line wiring segments are formed above the insulating layer provided on the data lines; and the first data-line wiring segments are formed directly under the second data-line wiring segments and are covered by the insulating layer.

2. The array substrate according to claim 1 , wherein the array substrate further comprises a common electrode and a pixel electrode in a display region of the array substrate;
wherein the pixel electrode is formed above the common electrode, the second gate-line wiring segments and the second data-line wiring segments are formed in a same layer as the pixel electrode is formed and are formed of a same material as the pixel electrode, wherein the first gate-line wiring segments and the first data-line wiring segments are formed in a same layer as the common electrode is formed and are formed of a same material as the common electrode; or
wherein the pixel electrode is formed under the common electrode, the second gate-line wiring segments and the second data-line wiring segments are formed in a same layer as the common electrode is formed and are formed of a same material as the common electrode, wherein the first gate-line wiring segments and the first data-line wiring segments are formed in a same layer as the pixel electrode is formed and are formed of same material as the pixel electrode.

3. The array substrate according to claim 1 , wherein a spacing between adjacent gate lines is between 20 μm and 30 μm, and a spacing between adjacent data lines is between 10 μm and 20 μm.

4. A method of manufacturing an array substrate, comprising the steps of:
in a gate line PAD region of the array substrate, forming gate-line wirings between adjacent gate lines, wherein the gate-line wirings are parallel to the adjacent gate lines and are electrically insulated from the adjacent gate lines; and
in a data line PAD region of the array substrate, forming data-line wirings between adjacent data lines, wherein the data-line wirings are parallel to the adjacent data lines and are electrically insulated from the adjacent data lines,
wherein both the gate-line wirings and the data-line wirings are conductive wiring segments;
wherein the gate-line wirings are configured to be used as restoring gate lines once gate lines of adjacent gate lines are scratched, and the data-line wirings are configured to be used as restoring data lines once the data lines of the adjacent data lines are scratched;
wherein the step of forming gate-line wirings between adjacent gate lines, wherein the gate-line wirings are parallel to the adjacent gate lines and are electrically insulated from the adjacent gate lines; and the step of forming the data-line wirings between adjacent data lines, wherein the data-line wirings are parallel to the adjacent data lines and are electrically insulated from the adjacent data lines, are performed in parallel and include;
depositing a first metal film on a substrate, and forming the data-line wirings spaced apart from each other, in the data line PAD region while forming the adjacent gate lines by a patterning process;
depositing an insulating layer on the first metal film and depositing a second metal film on the insulating layer; forming the gate-line wiring provided between the adjacent gate lines in the gate line PAD region while forming the adjacent data lines by a patterning process;
wherein the data-line wirings are formed between adjacent data lines, and the gate-line wirings are forming between adjacent gate lines.

5. A method of manufacturing an array substrate, comprising the steps of:
in a gate line PAD region of the array substrate,
forming gate-line wirings between adjacent gate lines, wherein the gate-line wirings are parallel to the adjacent gate lines and are electrically insulated from the adjacent gate lines; and
in a data line PAD region of the array substrate,
forming data-line wirings between adjacent data lines, wherein the data-line wirings are parallel to the adjacent data lines and are electrically insulated from the adjacent data lines, wherein both the gate-line wirings and the data-line wirings are conductive wiring segments;
wherein the gate-line wirings are configured to be used as restoring gate lines once gate lines of adjacent gate lines are scratched, and
the data-line wirings are configured to be used as restoring data lines once the data lines of the adjacent data lines are scratched; wherein the step of forming gate-line wirings between adjacent gate lines, wherein the gate-line wirings are parallel to the adjacent gate lines and are electrically insulated from the adjacent gate lines and the step of forming data-line wirings between adjacent data lines, wherein the data-line wirings are parallel to the adjacent data lines and are electrically insulated from the adjacent data lines, are performed in parallel and include:
depositing a first transparent conductive film on gate lines and data lines; forming first gate-line wiring segments in the gate line PAD region and first data-line wiring segments in the data line PAD region while forming a pixel electrode in a display region by a patterning process, wherein the first gate-line wiring segments are formed between adjacent gate lines, and the first data-line wiring segments are formed between adjacent data lines;
forming an insulating layer and a passivation layer on the array substrate in sequence from bottom to top and depositing a second transparent conductive film on the passivation layer; forming second gate-line wiring segments in the gate line PAD region and second data-line wiring segments in the data line PAD region while forming a common electrode in the display region by a patterning process, wherein the second gate-line wiring segments are formed between adjacent gate lines and the second data-line wiring segments are formed between adjacent data lines;
wherein the first gate-line wiring segments are formed directly under the second gate-line wiring segments, and the first data-line wiring segments are formed directly under the second data-line wiring segments.

6. A method of manufacturing an array substrate, comprising the steps o

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Display Tech Co

Inventors

• Liu Xiaowei
• Chen Xi
• Cai Zhenfei
• Liu Yao
• Li Liangliang
• Guo Zongjie

Classifications

• H10W20/01

  Manufacture or treatment · CPC title

• H01L27/1248

  Electricity · mapped topic

• H01L27/124

  Electricity · mapped topic

• G02F2001/13456

  Physics · mapped topic

• H01L27/1259

  Electricity · mapped topic