Array substrate, method of manufacturing the same, and display device

Patent metadata

Field	Value
Publication number	US-9817287-B2
Application number	US-201414314433-A
Country	US
Kind code	B2
Filing date	Jun 25, 2014
Priority date	Apr 30, 2014
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

The present disclosure relates to an array substrate, a method of manufacturing the same and a display device. The array substrate comprises a gate line PAD region and a data line PAD region. In the gate line PAD region of the array substrate, gate-line wirings, which are parallel to the gate lines and are electrically insulated from the gate lines, are provided between adjacent gate lines. In the data line PAD region of the array substrate, data-line wirings, which are parallel to the data lines and are electrically insulated from the data lines, are provided between adjacent data lines. Both of the gate-line wirings and the data-line wirings are conductive wiring segments. By forming the gate-line wirings and the data-line wirings in the PAD region, the ability of resisting scratch of the product can be improved while not deteriorating performance of display of the product.

First claim

What is claimed is:

1. An array substrate, comprising:
a gate line PAD region, wherein in the gate line PAD region of the array substrate, gate-line wirings, which are in parallel to gate lines and are electrically insulated from the gate lines, are provided between immediately-adjacent gate lines, and
a data line PAD region, wherein in the data line PAD region of the array substrate, data-line wirings, which are in parallel to data lines and are electrically insulated from the data lines, are provided between immediately-adjacent data lines,
wherein both of the gate-line wirings and the data-line wirings are conductive wiring segments,
wherein the gate-line wirings are configured to reduce steps caused between first locations where the gate lines are provided in the array substrate and second locations where no gate lines are provided in the array substrate, and which are configured to be used as restoring gate lines once the gate lines are scratched, and
wherein the data-line wirings are configured to reduce steps caused between first locations where the data lines are provided in the array substrate and second locations where no data lines are provided in the array substrate, and which are configured to be used as restoring data lines once the data lines are scratched.

2. The array substrate according to claim 1 ,
wherein the gate-line wirings include gate-line wiring segments provided on an insulating layer provided on the gate lines, the gate-line wiring segments being provided between immediately-adjacent gate lines, and
wherein the data-line wirings include data-line wiring segments provided on the insulating layer provided on the data lines, the data-line wiring segments being provided between immediately-adjacent data lines,
wherein the insulating layer covers the gate lines and the data lines.

3. The array substrate according to claim 2 , wherein the array substrate further comprises a pixel electrode, and the gate-line wiring segments and the data-line wiring segments are formed in a same layer as the pixel electrode is formed and are formed by a same material as that of the pixel electrode.

4. The array substrate according to claim 1 , wherein a spacing between immediately-adjacent gate lines is between 20 μm and 30 μm, and a spacing between immediately-adjacent data lines is between 10 μm and 20 μm.

5. A method of manufacturing an array substrate, comprising the steps of:
in a gate line PAD region of the array substrate, providing gate-line wirings between immediately-adjacent gate lines, wherein the gate-line wirings are in parallel to the gate lines and are electrically insulated from the gate lines, and
in a data line PAD region of the array substrate, providing data-line wirings between immediately-adjacent data lines, wherein the data-line wirings are in parallel to the data lines and are electrically insulated from the data lines,
wherein both of the gate-line wirings and the data-line wirings are conductive wiring segments,
wherein the gate-line wirings are configured to reduce steps caused between first locations where the gate lines are provided in the array substrate and second locations where no gate lines are provided in the array substrate, and which are configured to be used as restoring gate lines once the gate lines are scratched, and
wherein the data-line wirings are configured to reduce steps caused between first locations where the data lines are provided in the array substrate and second locations where no data lines are provided in the array substrate, and which are configured to be used as restoring data lines once the data lines are scratched.

6. The method according to claim 5 , wherein
the step of providing gate-line wirings, which are in parallel to the gate lines and are electrically insulated from the gate lines, between immediately-adjacent gate lines comprises:
forming the gate lines and an insulating layer in the gate line PAD region of the array substrate in sequence from bottom to top; and
forming the gate-line wirings spaced apart on the insulating layer, the gate-line wirings being located between immediately-adjacent gate lines and being in parallel to the gate lines; and
wherein the step of providing the data-line wirings, which are in parallel to the data lines and are electrically insulated from the data lines, between immediately-adjacent data lines comprises:
forming the data lines and the insulating layer in the data line PAD region of the array substrate in sequence from bottom to top; and

forming the data-line wirings spaced apart on the insulating layer, the data-line wirings being located between immediately-adjacent data lines and being in parallel to the data lines;
wherein both of the gate-line wirings and the data-line wirings are formed by conductive materials.

7. A display device, including the array substrate according to claim 1 .

8. The display device according to claim 7 , wherein the gate-line wirings include gate-line wiring segments provided on an insulating layer provided on the gate lines, the gate-line wiring segments being provided between immediately-adjacent gate lines, and wherein the data-line wirings include data-line wiring segments provided on the insulating layer provided on the data lines, the data-line wiring segments being provided between immediately-adjacent data lines, and wherein the insulating layer covers the gate lines and the data lines.

9. The display device according to claim 7 , wherein a spacing between immediately-adjacent gate lines is between 20 μm and 30 μm, and a spacing between immediately-adjacent data lines is between 10 μm and 20 μm.

10. The display device according to claim 8 , wherein the array substrate further comprises a pixel electrode, and the gate-line wiring segments and the data-line wiring segments are formed in a same layer as the pixel electrode is formed and are formed by a same material as that of the pixel electrode.

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Display Tech Co
• Boe Technology Group Co Ltd
• Beijing Boe Display Tech Co

Inventors

• Liu Xiaowei
• Chen Xi
• Cai Zhenfei
• Liu Yao
• Li Liangliang
• Guo Zongjie

Classifications

• H10W20/01

  Manufacture or treatment · CPC title

• H01L21/768

  Electricity · mapped topic

• G02F2001/13456

  Physics · mapped topic

• H01L27/1248

  Electricity · mapped topic

• H01L27/124

  Electricity · mapped topic