Semiconductor memory device and method for manufacturing same

Patent metadata

Field	Value
Publication number	US-10369715-B2
Application number	US-201715818793-A
Country	US
Kind code	B2
Filing date	Nov 21, 2017
Priority date	Jun 25, 2014
Publication date	Aug 6, 2019
Grant date	Aug 6, 2019

Abstract

According to one embodiment, the stacked body includes a plurality of stacked units and a first intermediate layer. Each of the stacked units includes a plurality of electrode layers and a plurality of insulating layers. Each of the insulating layers is provided between the electrode layers. The first intermediate layer is provided between the stacked units. The first intermediate layer is made of a material different from the electrode layers and the insulating layers. The plurality of columnar portions includes a channel body extending in a stacking direction of the stacked body to pierce the stacked body, and a charge storage film provided between the channel body and the electrode layers.

First claim

What is claimed is:

1. A semiconductor device comprising:
first memory cells provided in a first stacked body including a plurality of first electrode layers alternately stacked with a plurality of first insulating layers therebetween, the first memory cells having the first electrode layers as control gates and a first semiconductor portion as channels extending inside the first stacked body;
second memory cells provided in a second stacked body including a plurality of second electrode layers alternately stacked with a plurality of second insulating layers therebetween, the second memory cells having the second electrode layers as control gates and a second semiconductor portion as channels extending inside the second stacked body;
an interlayer cell having a conductive layer provided above the first stacked body and below the second stacked body and a third semiconductor portion provided between the first semiconductor portion and the second semiconductor portion, the third semiconductor portion having a tubular configuration, and the interlayer cell and the first and second memory cells being connected in series via the first to third semiconductor portions, and
an insulating film provided inside the third semiconductor portion having the tubular configuration, wherein
the interlayer cell is not used for storing data.

2. The device according to claim 1 , wherein
the first and second electrode layers include silicon and the first and second insulating layers include silicon oxide.

3. The device according to claim 2 , wherein
the conductive layer includes silicon.

4. The device according to claim 1 , wherein
the insulating film includes silicon oxide.

5. The device according to claim 1 , wherein
the first and second electrode layers and the conductive layer are provided around outer circumferential surfaces of the first to third semiconductor portions.

6. The device according to claim 1 , wherein
a lower end of a columnar member including the first to third semiconductor portions is connected to a source line and an upper end of the columnar member is connected to a bit line.

7. The device according to claim 1 , wherein
the first semiconductor portion and the second semiconductor portion have a tubular configuration and the insulating film is further provided inside at least one of the first semiconductor portion and the second semiconductor portion each having the tubular configuration.

8. A semiconductor device comprising:
first memory cells provided in a first stacked body including a plurality of first electrode layers alternately stacked with a plurality of first insulating layers therebetween, the first memory cells having the first electrode layers as control gates and a first semiconductor portion as channels extending inside the first stacked body;
second memory cells provided in a second stacked body including a plurality of second electrode layers alternately stacked with a plurality of second insulating layers therebetween, the second stacked body being stacked above the first stacked body, the second memory cells having the second electrode layers as control gates and a second semiconductor portion as channels extending inside the second stacked body and being electrically connected to the first semiconductor portion; and
an intermediate layer provided above the first stacked body and below the second stacked body, the intermediate layer being made of a material different from the first and second electrode layers and the first and second insulating layers, wherein
at least one of the first semiconductor portion and the second semiconductor portion has a tubular configuration and a core insulating film is provided inside the tubular configuration of at least one of the first semiconductor portion and the second semiconductor portion.

9. The device according to claim 8 , wherein
the first and second electrode layers include silicon and the first and second insulating layers include silicon oxide.

10. The device according to claim 8 , wherein
the material of the intermediate layer includes a metal element.

11. The device according to claim 8 , wherein
the core insulating film include silicon oxide.

12. The device according to claim 8 , wherein
the first and second semiconductor portions are included in a columnar member extending in a stacking direction of the first and second stacked bodies, a lower end of the columnar member being connected to a source line and an upper end of the columnar member being connected to a bit line.

13. The device according to claim 12 , wherein
the columnar member further includes a third semiconductor portion with a tubular configuration between the first semiconductor portion and the second semiconductor portion, the third semiconductor portion extending inside the intermediate layer and being electrically connected to the first and second semiconductor portions, the core insulating film being further provided inside the tubular configuration of the third semiconductor portion.

14. The device according to claim 8 , wherein
the first and second semiconductor portions are included in a columnar member piercing the first and second stacked bodies and the intermediate layer in a stacking direction of the first and second stacked bodies, and
a diameter of the columnar member in a direction perpendicular to the stacking direction is expanded at a height corresponding to the intermediate layer in the stacking direction.

15. A semiconductor device comprising:
a source layer;
first memory cells provided in a first stacked body located above the source layer, the first memory cells including a plurality of first control gate layers alternately stacked with a plurality of first insulating layers therebetween and a first channel body with a tubular configuration extending inside the first stacked body;
second memory cells provided in a second stacked body stacked above the first stacked body, the second memory cells including a plurality of second control gate layers alternately stacked with a plurality of second insulating layers therebetween and a second channel body with a tubular configuration extending inside the second stacked body;
a bit line provided above the second stacked body,
an intermediate layer interposed between the first stacked body and the second stacked body;
a first core insulator part provided inside the first channel body with the tubular configuration; and
a second core insulator part provided inside the second channel body with the tubular configuration, wherein
the first channel body and the second channel body extend in a stacking direction of the first and second stacked bodies and are electrically connected with each other between the source layer and the bit line via a third channel body passing the intermediate layer, the third channel body being bent in the stacking direction inside the intermediate layer, and
the first core insulator part has a first central axis extending in the stacking direction and the second core insulator part has a second central axis extending in the stacking direction, an upper end of the first central axis of the first core insulator part being apart from a lower end of the second central axis of the second core insulator part.

16. The device according to claim 15 , wherein
the intermediate layer is made of a material different from the first and second control gate layers and the first and second insulating layers.

17. The device according to claim 16 , wherein
the upper end of the first central axis of the first core insulator part

Assignees

• Toshiba Memory Corp

Inventors

• Sasaki Toshiyuki

Classifications

• H10P50/283

  by chemical means · CPC title

• H10W20/4446

  Refractory-metal alloys · CPC title

• H10W20/4441

  the principal metal being a refractory metal · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• B26B29/025 Primary

  Knife sheaths or scabbards · CPC title