Semiconductor device with a pick-up region

Patent metadata

Field	Value
Publication number	US-9111799-B2
Application number	US-201113109230-A
Country	US
Kind code	B2
Filing date	May 17, 2011
Priority date	May 25, 2010
Publication date	Aug 18, 2015
Grant date	Aug 18, 2015

Abstract

Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes a substrate doped with a first conductive type dopant, a plurality of stacked structures arranged side by side on the substrate and extending in a first direction, each of the stacked structures including gate electrodes spaced apart from each other, the plurality of stacked structures including a pair of stacked structures spaced apart from each other at a first interval in a second direction perpendicular to the first direction, and a pick-up region extending in the first direction in the substrate between the pair of stacked structures and doped with the first conductive type dopant.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate doped with a first conductive type dopant;
a plurality of stacked structures arranged side by side on the substrate and extending in a first direction, each of the stacked structures including gate electrodes spaced apart from each other, the plurality of stacked structures including a pair of stacked structures spaced apart from each other at a first interval in a second direction perpendicular to the first direction;
a plurality of semiconductor pillars penetrating the plurality of stacked structures to connect to the substrate;
a pick-up region extending in the first direction in the substrate between the pair of stacked structures and doped with the first conductive type dopant, wherein the semiconductor pillars do not overlap the pick-up region;
a pick-up contact pattern connected to the pick-up region and extending in the first direction between the pair of stacked structures, wherein the pair of stacked structures comprises first and second stacked structures, and wherein the plurality of stacked structures further comprise as third stacked structure adjacent to the second stacked structure and spaced apart from the second stacked structure at a second interval, in the second direction; and
a source contact pattern disposed on the substrate between the second and third stacked structures.

2. The semiconductor device of claim 1 , wherein a concentration of the first conductive type dopant is higher in the pick-up region than in the substrate.

3. The semiconductor device of claim 1 , wherein the pick-up contact pattern has a plate shape perpendicular to a top surface of the substrate, wherein the pick-up contact pattern has a length in the first direction and a width in the second direction, the length being larger than the width.

4. The semiconductor device of claim 1 , wherein
the second interval is narrower than the first interval,
the semiconductor device further comprising a common source region connected to the source contact pattern and extending in the first direction in the substrate between the second and third stacked structures, wherein the common source region has a second conductive type different from the first conductive type, and the common source region is spaced apart from the pick-up region.

5. The semiconductor device of claim 1 , further comprising insulation spacers on two sidewalls of each of the plurality of stacked structures, wherein the insulation spacers are spaced apart from the semiconductor pillars.

6. The semiconductor device of claim 1 , further comprising second conductive type remaining doping regions extending in the first direction in the substrate between the pair of stacked structures and disposed at two sides of the pick-up region.

7. The semiconductor device of claim 1 , further comprising an information storage layer between the plurality of semiconductor pillars and the gate electrodes.

8. The semiconductor device of claim 1 , wherein the pick-up region has a line shape having a length in the first direction and a width in the second direction, the length is larger than the width.

9. The semiconductor device of claim 1 , wherein the pick-up region is not formed in the substrate underneath the pair of stacked structures.

10. A semiconductor device, comprising:
a substrate doped with a first conductive type dopant;
a plurality of stacked structures arranged side by side on the substrate and extending in a first direction, each of the stacked structures including gate electrodes spaced apart from each other, the plurality of stacked structures including a pair of stacked structures spaced apart from each other at a first interval in a second direction perpendicular to the first direction;
a pick-up region extending in the first direction in the substrate between the pair of stacked structures and doped with the first conductive type dopant; and
a pick-up contact pattern connected to the pick-up region and extending in the first direction between the pair of stacked structures, wherein the pick-up contact pattern has a plate shape perpendicular to a top surface of the substrate, wherein the pair of stacked structures comprises first and second stacked structures; and the plurality of stacked structures further comprise a third stacked structure adjacent to the second stacked structure and spaced apart from the second stacked structure at a second interval in the second direction, the second interval being narrower than the first interval;
a second conductive type common source region extending in the first direction in the substrate between the second and third stacked structures; and
a source contact pattern connected to the common source region and extending in the first direction between the second and third stacked structures.

11. The semiconductor device of claim 10 , wherein the source contact pattern has a plate shape perpendicular to a top surface of the substrate.

12. The semiconductor device of claim 10 , wherein
the pick-up contact pattern comprises a main contact portion and auxiliary contact potions at two sides of the main contact portion, and wherein
the auxiliary contact portions comprise the same material as the source contact pattern.

13. A semiconductor device, comprising:
a substrate doped with a first conductive type dopant;
a plurality of stacked structures arranged side by side on the substrate and extending in a first direction, each of the stacked structures including gate electrodes spaced apart from each other, the plurality of stacked structures including a pair of stacked structures spaced apart from each other at a first interval in a second direction perpendicular to the first direction;
a plurality of semiconductor pillars penetrating the plurality of stacked structures to connect to the substrate;
a pick-up region extending in the first direction in the substrate between the pair of stacked structures and doped with the first conductive type dopant, wherein the semiconductor pillars do not overlap the pick-up region;
a pick-up contact pattern connected to the pick-up region and extending in the first direction between the pair of stacked structures; and
a common source region disposed on the substrate, wherein the common source region has a second conductive type different from the first conductive type, and wherein the common source region is spaced apart from the pick-up region.

14. The semiconductor device of claim 13 , wherein a concentration of the first conductive type dopant is higher in the pick-up region than in the substrate.

15. The semiconductor device of claim 13 , wherein the pick-up contact pattern has a plate shape perpendicular to a top surface of the substrate, wherein the pick-up contact pattern has a length in the first direction and a width in the second direction, the length being larger than the width.

16. The semiconductor device of claim 13 , wherein the pair of stacked structures comprises first and second stacked structures; and
the plurality of stacked structures further comprise a third stacked structure adjacent to the second stacked structure and spaced apart from the second stacked structure at a second interval in the second direction, the second interval being narrower than the first interval.

17. The semiconductor device of claim 13 , further comprising insulation spacers on two sidewalk of each of the plurality of stacked structures, wherein the insulation spacers are spaced apart from the semiconductor pillars.

18. The semiconductor device of claim 13 ,

Assignees

• Hwang Sung-Min
• Kim Kyoung-Hoon
• Kim Hansoo
• Shim Jae-Joo
• Jang Jaehoon
• Cho Wonseok
• Son Byoungkeun
• Cho Hoosung
• Samsung Electronics Co Ltd

Inventors

• Hwang Sung-Min
• Kim Kyoung-Hoon
• Kim Hansoo
• Shim Jae-Joo
• Jang Jaehoon
• Cho Wonseok
• Son Byoungkeun
• Cho Hoosung

Classifications

• H10D30/693 Primary

  Vertical IGFETs having charge trapping gate insulators · CPC title

• H10D30/0413

  of FETs having charge-trapping gate insulators, e.g. MNOS transistors · CPC title

• H10D30/69

  IGFETs having charge trapping gate insulators, e.g. MNOS transistors · CPC title

• H01L29/7926

  Electricity · mapped topic

• H01L29/66833

  Electricity · mapped topic