Devices and methods for power consumption control in powerline communications systems and apparatus

Patent metadata

Field	Value
Publication number	US-10367547-B2
Application number	US-201715816578-A
Country	US
Kind code	B2
Filing date	Nov 17, 2017
Priority date	Jan 18, 2013
Publication date	Jul 30, 2019
Grant date	Jul 30, 2019

Abstract

Systems and methods are provided for optimizing power consumption for power line communication (PLC). An example system may include a coupler that connects the system to a power line; an analog front end (AFE) for handling communications over the power line via the coupler; and a processor for controlling power consumption of the AFE. The processor may determine information regarding one or more control parameters of the analog front end (AFE), the information relating to powerline communications (PLC) over the power line; and based on the information, sets or adjusts the one or more control parameters of the analog front end (AFE), to control power consumption of the analog front end (AFE) during the powerline communications (PLC) over the power line. The analog front end (AFE) may then transmit or receive data over the power line using powerline communications (PLC), based on the one or more control parameters.

First claim

What is claimed is:

1. A system comprising:
a coupler that connects the system to a power line;
an analog front end (AFE) for handling communications over the power line via the coupler; and
a processor for controlling power consumption of the analog front end (AFE);
wherein:
the processor:
determines information regarding one or more control parameters of the analog front end (AFE), the information relating to powerline communications (PLC) over the power line; and
based on the information, sets or adjusts the one or more control parameters of the analog front end (AFE), to control power consumption of the analog front end (AFE) during the powerline communications (PLC) over the power line, wherein the processor sets the one or more control parameters of the analog front end (AFE) to ensure that noise and distortion caused by the analog front end (AFE) are adapted to noise from the PLC over the power line; and

the analog front end (AFE) transmits or receives data over the power line using the powerline communications (PLC), based on the one or more control parameters.

2. The system of claim 1 , wherein the processor:
determines current information regarding the one or more control parameters; and
re-adjusts at least one of the one or more control parameters of the analog front end (AFE) based on the current information, to re-adjust power consumption of the analog front end (AFE).

3. The system of claim 1 , wherein the processor determines the information regarding the one or more control parameters by:
determining a PLC channel condition; and
determining a related performance parameter required by an application or a network.

4. The system of claim 1 , wherein the processor determines the information regarding the one or more control parameters based on received information regarding a transmitter output power.

5. The system of claim 1 , wherein the processor determines the information regarding the one or more control parameters based on received information regarding impedance matching with the power line.

6. The system of claim 1 , wherein the processor sets or adjusts the one or more control parameters of the analog front end (AFE) to ensure that power consumption of the analog front end (AFE) meets particular performance criteria.

7. The system of claim 1 , wherein the processor computes the noise from the PLC over the power line as a function of a measured signal to noise ratio (SNR).

8. The system of claim 1 , wherein the processor computes the noise from the PLC over the power line as a function of tonemap and coding rate.

9. The system of claim 1 , wherein the processor sets or adjusts the one or more control parameters of the analog front end (AFE) to ensure that power consumption of the analog front end (AFE) is such that noise and distortion caused by the analog front end (AFE) are adapted to a target noise required for particular performance criteria.

10. The system of claim 9 , wherein the processor determines the particular performance criteria based on requirements of an application.

11. The system of claim 1 , wherein the analog front end (AFE) and the processor are implemented on a single integrated circuit (IC) chip.

12. The system of claim 1 , wherein the analog front end (AFE) and the processor are implemented on different integrated circuit (IC) chips.

13. The system of claim 1 , wherein the processor comprises a baseband processor.

14. The system of claim 1 , wherein the analog front end (AFE) comprises:
a transmit path comprising one or more transmit circuits; and
a receive path comprising one or more receive circuits.

15. The system of claim 14 , wherein the one or more transmit circuits comprise one or more of: an analog converter (DAC), a reconstruction filter, a programmable gain amplifier (PGA), and a line driver.

16. The system of claim 14 , wherein the one or more receive circuits comprise one or more of: a low noise amplifier (LNA), programmable gain amplifier (PGA), an anti-aliasing filter, and an analog to digital converter (ADC).

17. The system of claim 1 , wherein the analog front end (AFE) comprises a control circuit for supporting control functions by the processor when controlling power consumption in the analog front end (AFE).

18. The system of claim 17 , wherein the control circuit is connected with the processor via a Serial Peripheral Interface (SPI).

19. A system comprising:
a coupler that connects the system to a power line;
an analog front end (AFE) for handling communications over the power line via the coupler; and
a processor for controlling power consumption of the analog front end (AFE);
wherein:
the processor:
determines information regarding one or more control parameters of the analog front end (AFE), the information relating to powerline communications (PLC) over the power line; and
based on the information, sets or adjusts the one or more control parameters of the analog front end (AFE), to control power consumption of the analog front end (AFE) during the powerline communications (PLC) over the power line, wherein the processor determines the information regarding the one or more control parameters by:
determining a PLC channel condition; and
determining a related performance parameter required by an application or a network; and

the analog front end (AFE) transmits or receives data over the power line using the powerline communications (PLC), based on the one or more control parameters.

20. The system of claim 19 , wherein the processor:
determines current information regarding the one or more control parameters; and
re-adjusts at least one of the one or more control parameters of the analog front end (AFE) based on the current information, to re-adjust power consumption of the analog front end (AFE).

21. The system of claim 19 , wherein the processor determines the information regarding the one or more control parameters based on received information regarding a transmitter output power.

22. The system of claim 19 , wherein the processor determines the information regarding the one or more control parameters based on received information regarding impedance matching with the power line.

23. The system of claim 19 , wherein the processor sets or adjusts the one or more control parameters of the analog front end (AFE) to ensure that power consumption of the analog front end (AFE) meets particular performance criteria.

24. The system of claim 19 , wherein the processor sets or adjusts the one or more control parameters of the analog front end (AFE) to ensure that power consumption of the analog front end (AFE) is such that noise and distortion caused by the analog front end (AFE) are adapted to a target noise required for particular performance criteria.

25. The system of claim 24 , wherein the processor determines the particular performance criteria based on requirements of an application.

26. The system of claim 19 , wherein the analog front end (AFE) and the processor are implemented on a single integrated circuit (IC) chip.

27. The system of claim 19 , wherein the analog front end (AFE) and the processor are implemented on different integrated circuit (IC) chips.

28. The system of claim 19 , wherein the processor comprises a baseband processor.

29. The system of claim 19 , wherein the analog front end (AFE) comprises:
a transmit path

Assignees

• Maxlinear Asia Singapore PTE LTD
• Maxlinear Asia Singapore Private Ltd

Inventors

• Smaini Lydi
• Rouxel Alexandre

Classifications

• H04B2203/5495

  having measurements and testing channel · CPC title

• H04B3/56

  Circuits for coupling, blocking, or by-passing of signals · CPC title

• H04B2203/5416

  by adding signals to the wave form of the power source · CPC title

• H04B3/542

  the information being in digital form · CPC title

• H04B2203/5425

  improving S/N by matching impedance, noise reduction, gain control · CPC title