Digital synthesizer, communication unit and method therefor

Patent metadata

Field	Value
Publication number	US-10367464-B2
Application number	US-201715645112-A
Country	US
Kind code	B2
Filing date	Jul 10, 2017
Priority date	Oct 27, 2016
Publication date	Jul 30, 2019
Grant date	Jul 30, 2019

Abstract

A digital synthesizer is described that comprises: a ramp generator configured to generate a signal of frequency control words, FCW, that describes a desired frequency modulated continuous wave; a digitally controlled oscillator, DCO configured to receive the FCW signal; a feedback loop; and a phase comparator coupled to the ramp generator and configured to compare a phase of the FCW output from the ramp generator and a signal fed back from the DCO via the feedback loop and output a N-bit oscillator control signal. The digital synthesizer comprises a gain circuit coupled to a multiplier located between the ramp generator and the DCO and configured to apply at least one gain from a plurality of selectable gains to the N-bit oscillator control signal that set a selectable loop gain of the digital synthesizer and thereby set a selectable loop bandwidth; and
calculate and apply a gain offset dependent upon the selected gain that is adapted when the selected gain is changed.

First claim

The invention claimed is:

1. A digital synthesizer comprising:
a ramp generator configured to generate a signal of frequency control words, FCW, that describes a desired frequency modulated continuous wave;
a digitally controlled oscillator, DCO configured to receive the FCW signal;
a feedback loop; and
a phase comparator coupled to the ramp generator and configured to compare a phase of the FCW output from the ramp generator and a signal fed back from the DCO via the feedback loop and output a N-bit oscillator control signal;
wherein the digital synthesizer comprises a gain circuit coupled to a multiplier located between the ramp generator and the DCO and configured to:
apply at least one gain from a plurality of selectable gains to the N-bit oscillator control signal that set a selectable loop gain of the digital synthesizer and thereby set a selectable loop bandwidth;
calculate and apply a first gain offset dependent upon the selected gain that is adapted when the selected gain is changed during a transition from high bandwidth to low bandwidth operation; and
calculate and apply a second gain offset dependent upon the selected gain that is adapted when the selected gain is changed during a transition from low bandwidth to high bandwidth operation, and

wherein the ramp generator is configured to provide a gain selector signal to the gain circuit to select the at least one gain from the plurality of selectable gains.

2. The digital synthesizer of claim 1 , wherein the first and second gain offsets added to the gain-adjusted N-bit oscillator control signal are based on a previously added offset.

3. The digital synthesizer of claim 2 , wherein the first and second gain offsets added to the gain-adjusted N-bit oscillator control signal are updated on each successive ramp-up or ramp down signal generated by the ramp generator.

4. The digital synthesizer of claim 1 , wherein the plurality of selectable gains comprises a first gain that sets a first loop gain causing a first loop bandwidth, and a second gain that sets a second loop gain causing a second loop bandwidth that is a higher loop bandwidth than that caused by the first gain.

5. The digital synthesizer of claim 1 , wherein the ramp generator is configured to provide a gain selector signal to the gain circuit to select the at least one gain from the plurality of selectable gains during a ramp reset period.

6. The digital synthesizer of claim 1 wherein the gain circuit is located within a gear shifting circuit.

7. The digital synthesizer of claim 1 , wherein the gain circuit is located within a loop filter located between the ramp generator and DCO and configured to impart a filter frequency response to the N-bit oscillator control signal, wherein the filter frequency response is adapted in conjunction with the selectable gain.

8. The digital synthesizer of claim 7 , wherein the gain circuit is configured to effect a loop gain change by adapting a proportional part operation of the loop filter.

9. The digital synthesizer of claim 1 , wherein the gain circuit applies the selected gain dynamically during a generation of frequency modulated continuous wave radar ramp-up or ramp-down signal when the PLL is locked.

10. The digital synthesizer of claim 1 , wherein a second gain of the gain circuit is selected during a frequency reset of the digital synthesizer.

11. The digital synthesizer of claim 1 , wherein first and second gains of the gain circuit are selected and switched to support an increasing or a decreasing frequency of the digital synthesizer.

12. A communication unit having a digital synthesizer comprising:
a ramp generator configured to generate a signal of frequency control words, FCW, that describes a desired frequency modulated continuous wave;
a digitally controlled oscillator, DCO configured to receive the FCW signal;
a feedback loop; and
a phase comparator coupled to the ramp generator and configured to compare a phase of the FCW output from the ramp generator and a signal fed back from the DCO via the feedback loop and output a N-bit oscillator control signal;
wherein the digital synthesizer comprises a gain circuit coupled to a multiplier located between the ramp generator and the DCO and configured to:
apply at least one gain from a plurality of selectable gains to the N-bit oscillator control signal that sets a selectable loop gain of the digital synthesizer and thereby set a selectable loop bandwidth; and
calculate and apply a first gain offset dependent upon the selected gain that is adapted when the selected gain is changed during a transition from high bandwidth to low bandwidth operation;
calculate and apply a second gain offset dependent upon the selected gain that is adapted when the selected gain is changed during a transition from low bandwidth to high bandwidth operation, and

wherein the ramp generator is configured to provide a gain selector signal to the gain circuit to select the at least one gain from the plurality of selectable gains.

13. The communication unit of claim 12 , wherein the first and second gain offsets added to the gain-adjusted N-bit oscillator control signal are based on a previously added offset.

14. The communication unit of claim 13 , wherein the first and second gain offsets added to the gain-adjusted N-bit oscillator control signal are updated on each successive ramp-up or ramp down signal generated by the ramp generator.

15. The communication unit of claim 12 , wherein the plurality of selectable gains comprises a first gain that sets a first loop gain causing a first loop bandwidth, and a second gain that sets a second loop gain causing a second loop bandwidth that is a higher loop bandwidth than that caused by the first gain.

16. The communication unit of claim 12 , wherein the ramp generator is configured to provide a gain selector signal to the gain circuit to select the at least one gain from the plurality of selectable gains during a ramp reset period.

17. The communication unit of claim 12 , wherein the gain circuit is located within a loop filter located between the ramp generator and DCO and configured to impart a filter frequency response to the N-bit oscillator control signal, wherein the filter frequency response is adapted in conjunction with the selectable gain.

18. A method for maintaining an open loop gain of a digitally controlled oscillator, DCO, feedback loop as substantially constant, the method comprising:
generating a signal of frequency control words, FCW, that describes a desired frequency modulated continuous wave, wherein the generating is performed by a ramp generator;
comparing a phase of the FCW signal with a signal fed back from an output of the DCO at a phase comparator and outputting a N-bit oscillator control signal from the phase comparator;
selecting at least one gain from a plurality of selectable gains, wherein the at least one gain is selected based on a gain selector signal received from the ramp generator;
applying the selected at least one gain from a plurality of selectable gains to the N-bit oscillator control signal to set a selectable loop gain of the digital synthesizer and thereby set a selectable loop bandwidth; and
calculating and applying a first gain offset dependent upon the selected gain that is adapted when the selected gain is changed during a transition from high bandwidth to low bandwidth operation;
calculating and applying a second gain offset dependent upon the selected gain that is adapted when the selected gain is changed during a transition from low bandwidth to high ba

Assignees

• Nxp Usa Inc

Inventors

• Salle Didier
• Doare Olivier Vincent
• Goumballa Birama
• Pavao Moreira Cristian

Classifications

• H03L2207/50

  All digital phase-locked loop · CPC title

• H03L7/1075

  by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth (H03L7/1072 takes precedence) · CPC title

• H03L7/0992

  comprising a counter or a frequency divider · CPC title

• H03L7/091

  the phase or frequency detector using a sampling device (H03L7/087 takes precedence) · CPC title

• G01S13/343

  using sawtooth modulation · CPC title