Phase locked loop with reduced noise

Patent metadata

Field	Value
Publication number	US-9893876-B2
Application number	US-201615156584-A
Country	US
Kind code	B2
Filing date	May 17, 2016
Priority date	May 20, 2015
Publication date	Feb 13, 2018
Grant date	Feb 13, 2018

Abstract

A phase locked loop, comprising: a phase detector configured to determine a phase difference (Δφ) between a reference signal and a feedback signal; a loop filter configured to perform a filtering operation on a signal derived from the phase difference, and to provide a control signal; a frequency controlled oscillator configured to receive the control signal and provide an output signal with a frequency that varies according to the control signal; wherein a low-pass filter is provided between the phase detector and the loop filter and/or between the loop filter and the frequency controlled oscillator to reduce quantization noise from the phase detector.

First claim

The invention claimed is:

1. A phase locked loop, comprising:
a phase detector configured to determine a phase difference between a reference signal and a feedback signal;
a digital loop filter configured to perform a filtering operation on a signal derived from the phase difference and to provide three different control signals;
a digitally controlled oscillator configured to receive the three different control signals and provide an output signal with a frequency that varies according to the three different control signals; and
a low-pass filter is provided between the phase detector and the digital loop filter and configured to reduce quantization noise from the phase detector by having a cut-off frequency that is greater than a bandwidth of the phase locked loop.

2. The phase locked loop of claim 1 , wherein the phase locked loop has a bandwidth defined by the characteristics of the phase detector, the digital loop filter and the digitally controlled oscillator.

3. The phase locked loop of claim 2 , wherein the low-pass filter has a cut-off frequency at least 1.2 times the bandwidth of the phase locked loop.

4. The phase locked loop of claim 2 , wherein the low-pass filter has a cut-off frequency that is at least 100 kHz greater than the bandwidth of the phase locked loop.

5. The phase locked loop of claim 1 , wherein the low-pass filter comprises a first order Infinite Impulse Response (IIR) filter.

6. The phase locked loop of claim 5 , wherein the first order IIR filter further comprises:
a shift multiplier in a forward path thereof, configured to multiply by an integer power of two.

7. The phase locked loop of claim 1 , wherein the digital loop filter further comprises:
an integral path comprising an integrator.

8. The phase locked loop of claim 7 , wherein the digital loop filter further comprises:
a proportional path.

9. The phase locked loop of claim 8 , wherein the phase locked loop is configured with a proportional gain factor k p in the proportional path and an integral gain factor k i prior to the integrator in the integral path, wherein:
k p ≦2 −12 ; k i ≦2 −18 .

10. The phase locked loop of claim 1 , wherein the digitally controlled oscillator further comprises:
a switched capacitor LC oscillator.

11. A receiver comprising the phase locked loop of claim 1 .

12. The receiver of claim 11 , wherein the receiver is a satellite radio receiver.

13. The phase locked loop of claim 1 , wherein the digital loop filter is configured to provide a process voltage temperature control signal to the digitally controlled oscillator.

14. The phase locked loop of claim 1 , wherein the digital loop filter is configured to provide an acquisition control signal to the digitally controlled oscillator.

15. The phase locked loop of claim 1 , wherein the digital loop filter is configured to provide a tracking signal to the digitally controlled oscillator.

16. The phase locked loop of claim 1 , wherein the digital loop filter is configured to provide the three different control signals to respective switched capacitor banks of the digitally controlled oscillator.

17. A phase locked loop, comprising:
a phase detector configured to determine a phase difference between a reference signal and a feedback signal;
a digital loop filter configured to perform a filtering operation on a signal derived from the phase difference and to provide three different control signals;
a digitally controlled oscillator configured to receive the three different control signals and provide an output signal with a frequency that varies according to the three different control signals; and
a low-pass filter is provided between the digital loop filter and the digitally controlled oscillator and configured to reduce quantization noise from the phase detector by having a cut-off frequency that is greater than a bandwidth of the phase locked loop.

Assignees

• Nxp Bv

Inventors

• Moehlmann Ulrich

Classifications

• H04B1/12

  Neutralising, balancing, or compensation arrangements · CPC title

• H03L7/093 Primary

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title

• H03L2207/50

  All digital phase-locked loop · CPC title

• H03L7/091

  the phase or frequency detector using a sampling device (H03L7/087 takes precedence) · CPC title

• H03L7/0991

  the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider (H03L7/0995 takes precedence; fixed oscillators with means for selecting among various phases H03L7/0814) · CPC title